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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4513/4514 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D converter. The various microcomputers in the 4513/4514 Group include variations of the built-in memory type and package as shown in the table below.
FEATURES
qMinimum instruction execution time ................................ 0.75 s (at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0 V to 5.5 V) qSupply voltage * Middle-speed mode ...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) * High-speed mode ...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask ROM version and One Time PROM version) ...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) ROM (PROM) size (! 10 bits) 2048 words 4096 words 4096 words 6144 words 8192 words 8192 words 6144 words 8192 words 8192 words
qTimers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 4 ...................................... 8-bit timer with a reload register qInterrupt ........................................................................ 8 sources qSerial I/O ....................................................................... 8 bit-wide qA-D converter .................. 10-bit successive comparison method qVoltage comparator ........................................................ 2 circuits qWatchdog timer ................................................................. 16 bits qVoltage drop detection circuit qClock generating circuit (ceramic resonator) qLED drive directly enabled (port D)
APPLICATION
Microwave oven, rice cooker, audio, telephone, office equipment
Product M34513M2-XXXSP/FP * M34513M4-XXXSP/FP * M34513E4SP/FP * (Note) M34513M6-XXXFP ** M34513M8-XXXFP ** M34513E8FP ** (Note) M34514M6-XXXFP * M34514M8-XXXFP * M34514E8FP * (Note)
Note: shipped in blank * : Under development **: Under planning
RAM size (! 4 bits) 128 words 256 words 256 words 384 words 384 words 384 words 384 words 384 words 384 words
Package SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A 32P6B-A 32P6B-A 32P6B-A 42P2R-A 42P2R-A 42P2R-A
ROM type Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW) 4513 Group
D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P13 P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+ AIN0/CMP0P31/INT1 P30/INT0 VDCE VDD
M34513Mx-XXXSP
29 P13 26 P10 28 P12 25 P03 27 P11
Outline 32P4B
D3 1 D4 D5 3
2
31 D1
30 D0
M34513E4SP
32 D2 11
24 P02 23 P01 22 P00 21
D6/CNTR0 4 D7/CNTR1 5 P20/SCK 6 P21/SOUT P22/SIN 8
7
M34513Mx-XXXFP M34513ExFP
AIN3/CMP1+ 20 AIN2/CMP119 18
AIN1/CMP0+ AIN0/CMP0-
17 P31/INT1
Outline 32P6B-A
2
P30/INT0 16
VDD 14
VSS 13
XIN 12
CNVSS 10
RESET 9
XOUT
VDCE 15
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW) 4514 Group
P13 1 D0 2 D1 3 D2 4 D3 5 D4 6
42 P12 41 P11 40 P10 39 P03 38 P02 37 P01 36 P00 35 P43/AIN7 34 P42/AIN6 33 P41/AIN5 32 P40/AIN4 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP027 P33 26 P32 25 P31/INT1 24 P30/INT0 23 VDCE 22 VDD
M34514Mx-XXXFP
M34514E8FP
D5 7 D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK P21/SOUT
14 15
P22/SIN 16 RESET 17 CNVSS 18 XOUT
19
XIN 20 VSS 21
Outline 42P2R-A
3
4
4 3 2 8
4
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I/O port
Port P0 | [ Port P1 go 1 Port P2 Port P3 Port D
.
Internal peripheral functions
Voltage comparator (2 circuits) System clock generating circuit XIN-XOUT
BLOCK DIAGRAM (4513 Group)
Timer
Timer 1 (8 bits)
Timer 2 (8 bits)
Timer 3 (8 bits) Voltage drop detection circuit
Timer 4 (8 bits)
Watchdog timer (16 bits)
Memory
ROM
2048, 4096,6144, 8192 words x 10 bits
A-D converter (10 bits ! 4 ch)
4500 Series CPU core
ALU (4 bits)
Serial I/O (8 bits ! 1)
RAM
128, 256, 384 words x 4 bits
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
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I/O port
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port D
Internal peripheral functions
Voltage comparator (2 circuits) System clock generating circuit XIN--XOUT
BLOCK DIAGRAM (4514 Group)
Timer
Timer 1 (8 bits)
Timer 2 (8 bits)
Timer 3 (8 bits) Voltage drop detection circuit
Timer 4 (8 bits)
Watchdog timer (16 bits)
Memory
ROM
6144, 8192 words x 10 bits
A-D converter (10 bits ! 8 ch)
4500 Series CPU core
ALU (4 bits)
Serial I/O (8 bits ! 1)
RAM
384 words x 4 bits
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
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4513/4514 Group
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter 4513 Group Number of 4514 Group basic instructions Minimum instruction execution time M34513M2 Memory sizes ROM M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 RAM M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 I/O (Input is Input/Output D0-D7 examined by ports skip decision) P00-P03 I/O P10-P13 I/O P20-P22 Input P30-P33 I/O P40-P43 P50-P53 CNTR0 CNTR1 INT0 INT1 Timer 1 Timer 2 Timer 3 Timer 4 I/O I/O I/O I/O Input Input Function 123 128 0.75 s (at 4.0 MHz oscillation frequency, in high-speed mode) 2048 words ! 10 bits 4096 words ! 10 bits 6144 words ! 10 bits 8192 words ! 10 bits 6144 words ! 10 bits 8192 words ! 10 bits 128 words ! 4 bits 256 words ! 4 bits 384 words ! 4 bits 384 words ! 4 bits 384 words ! 4 bits 384 words ! 4 bits Eight independent I/O ports; ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. 4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port; The 4513 Group does not have this port. 4-bit I/O port with a direction register; The 4513 Group does not have this port. 1-bit I/O; CNTR0 pin is also used as port D6. 1-bit I/O; CNTR1 pin is also used as port D7. 1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function. 1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 10-bit wide, This is equipped with an 8-bit comparator function. 2 circuits (CMP0, CMP1) 8-bit ! 1 8 (two for external, four for timer, one for A-D, and one for serial I/O) 1 level 8 levels CMOS silicon gate 32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A) 42-pin plastic molded SSOP (42P2R-A) -20 C to 85 C 2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the electrical characteristics because the supply voltage depends on the oscillation frequency.) 1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transistors in the cut-off state) 3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 A (at room temperature, VDD = 5 V, output transistors in the cut-off state)
Timers
A-D converter Voltage comparator Serial I/O Sources Interrupt Nesting Subroutine nesting Device structure 4513 Group Package 4514 Group Operating temperature range Supply voltage Active mode Power dissipation (typical value) RAM back-up mode
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin VDD VSS VDCE Name Power supply Ground Voltage drop detection circuit enable CNVSS Reset input Input/Output -- -- Input Function Connected to a plus power supply. Connected to a 0 V power supply. VDCE pin is used to control the operation/stop of the voltage drop detection circuit. When "H" level is input to this pin, the circuit is operating. When "L" level is inpu to this pin, the circuit is stopped. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the watchdog timer causes the system to be reset or system reset is performed by the voltage drop detection circuit, the RESET pin outputs "L" level. I/O pins of the system clock generating circuit. XIN and XOUT can be connected to ceramic resonator. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to "1." The output structure is N-channel open-drain. Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. 3-bit input port. Ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. 4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the specified bit to "1." The output structure is N-channel open-drain. Ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port. For input use, set the latch of the specified bit to "1." The output structure is N-channel open-drain. Ports P40-P43 are also used as analog input pins AIN4-AIN7, respectively. The 4513 Group does not have port P4. 4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O function. For input use, set the direction register to "0." For output use, set the direction regiser to "1." The output structure is CMOS. The 4513 Group does not have port P5. Analog input pins for A-D converter. AIN0-AIN3 are also used as comparator input pins and AIN4-AIN7 are also used as port P4. The 4513 Group does not have AIN4-AIN7. CNTR0 pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 underflow signal divided by 2. CNTR0 pin is also used as port D6. CNTR1 pin has the function to input the clock for the timer 4 event counter, and to output the timer 3 underflow signal divided by 2. CNTR1 pin is also used as port D7. INT0, INT1 pins accept external interrupts. They also accept the input signal to return the system from the RAM back-up state. INT0, INT1 pins are also used as ports P30 and P31, respectively. SIN pin is used to input serial data signals by software. SIN pin is also used as port P22. SOUT pin is used to output serial data signals by software. SOUT pin is also used as port P21. SCK pin is used to input and output synchronous clock signals for serial data transfer by software. SCK pin is also used as port P20. CMP0-, CMP0+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software. CMP0-, CMP0+ pins are also used as AIN0 and AIN1. CMP1-, CMP1+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software. CMP1-, CMP1+ pins are also used as AIN2 and AIN3.
CNVSS RESET
-- I/O Input Output I/O
XIN XOUT D0-D7
System clock input System clock output I/O port D (Input is examined by skip decision.) I/O port P0 I/O port P1 Input port P2 I/O port P3
P00-P03 P10-P13 P20-P22 P30-P33
I/O I/O Input I/O
P40-P43
I/O port P4
I/O
P50-P53
I/O port P5
I/O
AIN0-AIN7
Analog input
Input
CNTR0
Timer input/output
I/O
CNTR1
Timer input/output
I/O
INT0, INT1
Interrupt input
Input
SIN SOUT SCK
Serial data input Serial data output Serial I/O clock input/output Voltage comparator input Voltage comparator input
Input Output I/O
CMP0CMP0+ CMP1CMP1+
Input
Input
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MULTIFUNCTION
Pin D6 D7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Pin CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Multifunction D6 D7 P20 P21 P22 P30 P31 Pin AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Multifunction CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Pin CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Multifunction AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43
Notes 1: Pins except above have just single function. 2: The input of D6, D7, P20-P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40-P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, and AIN0-AIN7 are selected. 3: The 4513 Group does not have P40/AIN4-P43/AIN7.
CONNECTIONS OF UNUSED PINS
Pin XOUT VDCE D0-D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4-P43/AIN7 P50-P53 (Note 1) Connection Open (when using an external clock). Connect to VSS. Connect to VSS, or set the output latch to "0" and open. Connect to VSS.
Notes 1: After system is released from reset, port P5 is in a input mode (direction register FR0 = 00002) 2: When the P00-P03 and P10-P13 are connected to VSS, turn off their pull-up transistors (register PU0i="0") and also invalidate the key-on wakeup functions (register K0i="0") by software. When these pins are connected to VSS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i="1") by software, or set the output latch to "0." Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.) (Note when the output latch is set to "0" and pins are open) q After system is released from reset, port is in a high-impedance state until it is set the output latch to "0" by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state. q To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
Connect to VSS, or set the output latch to "0" and open. Connect to VSS, or set the output latch to "0" and open. When the input mode is selected by software, pull-up to VDD through a resistor or pull-down to VDD. When selecting the output mode, open. Connect to VSS.
AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P00-P03 P10-P13
Open or connect to VSS (Note 2) Open or connect to VSS (Note 2)
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT FUNCTION
Port Port D Pin D0-D5 D6/CNTR0 D7/CNTR1 P00-P03 Input Output I/O (8) I/O (4) Output structure N-channel open-drain I/O unit 1 Control instructions SD, RD SZD CLD OP0A IAP0 Control registers W6 PU0, K0 Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Remark
Port P0
N-channel open-drain
4
Port P1
P10-P13
I/O (4)
N-channel open-drain
4
OP1A IAP1
PU0, K0
Port P2
Port P3 (Note 1) Port P4 (Note 2) Port P5 (Note 2)
P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4 -P43/AIN7 P50-P53
Input (3) I/O (4) I/O (4) I/O (4) N-channel open-drain
3
IAP2
J1
4
OP3A IAP3 OP4A IAP4 OP5A IAP5
I1, I2
Built-in key-on wakeup function (P30/INT0, P31/INT1)
N-channel open-drain CMOS
4 4
Q2 FR0
Notes 1: The 4513 Group does not have P32 and P33. 2: The 4513 Group does not have these ports.
DEFINITION OF CLOCK AND CYCLE
q System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control register MR. Table Selection of system clock Register MR MR3 0 1
System clock f(XIN) f(XIN)/2
Note: f(XIN)/2 is selected after system is released from reset. q Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS
K00
Key-on wakeup input IAP0 instruction Register A
Ai DQ T
Pull-up transistor
PU00
P00,P01
OP0A instruction
K01
Key-on wakeup input IAP0 instruction Register A
Ai DQ T
Pull-up transistor
PU01
P02,P03
OP0A instruction
K02
Key-on wakeup input IAP1 instruction Register A
Ai DQ
Pull-up transistor
PU02
P10,P11
OP1A instruction T
K03
Key-on wakeup input IAP1 instruction Register A
Ai DQ
Pull-up transistor
PU03
P12,P13
OP1A instruction T
* *i
This symbol represents a parasitic diode on the port. represents 0, 1, 2, or 3.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
IAP2 instruction Register A
Synchronous clock input for serial transfer
J11
0
P20/SCK
Synchronous clock output for serial transfer J10
1
IAP2 instruction Register A
J11
0
P21/SOUT
Serial data output
1
Serial data input IAP2 instruction Register A
P22/SIN
Key-on wakeup input External interrupt circuit IAP3 instruction Register A Ai OP3A instruction D T Q
P30/INT0,P31/INT1
IAP3 instruction Register A Ai OP3A instruction D T Q
P32,P33
This symbol represents a parasitic diode on the port. * * Applied potential to ports P20--P22 must be VDD. * i represents 0, 1, 2, or 3. * The 4513 Group does not have ports P32, P33.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
Q1
Decoder
Analog input
AIN0/CMP0-
Q30 CMP0
+
Q32 Q1
Decoder
Analog input
AIN1/CMP0+
Q1
Decoder
Analog input
AIN2/CMP1-
Q31 CMP1
+
Q33 Q1
Decoder
Analog input
AIN3/CMP1+
IAP4 instruction Register A Ai OP4A instruction DQ T Q1
P40/AIN4-P43/AIN7
Decoder
Analog input
This symbol represents a parasitic diode on the port. * * i represents 0, 1, 2, or 3. * The 4513 Group does not have port P4.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
Direction register FR0i
Ai D T Q
P50-P53
OP5A instruction
Register A IAP5 instruction
Register Y
Decoder
Skip decision (SZD instruction)
S R Q
D0-D5
SD instruction RD instruction
Skip decision (SZD instruction) Clock input for timer 2 event count Register Y Decoder
S R Q
SD instruction RD instruction Timer 1 underflow signal output
W60 0 1
D6/CNTR0
1/2
Skip decision (SZD instruction) Clock input for timer 4 event count Register Y Decoder
S R Q
SD instruction RD instruction Timer 3 underflow signal output
W62 0 1
D7/CNTR1
1/2
This symbol represents a parasitic diode on the port. * * Applied potential to ports D0-D7 must be 12 V. * i represents 0, 1, 2, or 3. * The 4513 Group does not have port P5.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
I12 Falling
0
One-sided edge detection circuit
I11
0
P30/INT0
1 1
EXF0 Both edges detection circuit Wakeup Skip SNZI0
External 0 interrupt
Rising
I22 Falling
0
One-sided edge detection circuit
I21
0
P31/INT1
1 1
EXF1 Both edges detection circuit Wakeup Skip SNZI1
External 1 interrupt
Rising
External interrupt circuit structure
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
FUNCTION BLOCK OPERATIONS CPU
(CY)

(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.
(M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction.
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3).
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
Register B
TAB instruction
Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2 DR1DR0 A3 A2 A1 A0
Low-order 4bits Register A (4) Middle-order 4 bits Register B (4)
Immediate field value p
The contents of The contents of register D register A
Fig. 4 TABP p instruction execution example
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
(PC) (SK0) (SP) 7
Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.
Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).
Register Y (4) Register X (4)
Specifying RAM digit
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D7 D6 D5 D4 D0
0
1
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34514M8/E8. Table 1 ROM size and pages Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 ROM size (! 10 bits) 2048 words 4096 words 6144 words 8192 words 6144 words 8192 words Pages 16 (0 to 15) 32 (0 to 31) 48 (0 to 47) 64 (0 to 63) 48 (0 to 47) 64 (0 to 63)
98 000016 007F16 008016 00FF16 010016 017F16 018016
7
6
5
4
3
2
10 Page 0
Interrupt address page Subroutine special page
Page 1 Page 2 Page 3
0FFF16
Page 31
1FFF16
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
Page 63
Fig. 10 ROM map of M34514M8/E8
98765 430 1 2 008016 External 0 interrupt address 008216 008416 008616 008816 008A16 008C16 008E16 External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address Timer 4 interrupt address A-D interrupt address Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 128 words 256 words 384 words 384 words 384 words 384 words RAM size ! 4 bits (512 bits) ! 4 bits (1024 bits) ! 4 bits (1536 bits) ! 4 bits (1536 bits) ! 4 bits (1536 bits) ! 4 bits (1536 bits)
RAM 384 words ! 4 bits (1536 bits)
Register Z
0
1 15 0 1 2 3 4 5 6 7
Register X 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M34513M6 M34513M8/E8 15 M34514M6 Z=0, X=0 to 15 M34514M8/E8 Z=1, X=0 to 7
Register Y
384 words 256 words 128 words
M34513M4/E4 Z=0, X=0 to 15 M34513M2 Z=0, X=0 to 7
Fig. 12 RAM map
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)
Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 5 6 7 8 External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A-D interrupt Serial I/O interrupt
Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 4 underflow Completion of A-D conversion Completion of serial I/O transfer
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed.
Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Request flag EXF0 EXF1 External 1 interrupt T1F Timer 1 interrupt T2F Timer 2 interrupt T3F Timer 3 interrupt T4F Timer 4 interrupt ADF A-D interrupt SIOF Serial I/O interrupt Interrupt name External 0 interrupt Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Enable bit V10 V11 V12 V13 V20 V21 V22 V23
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
Table 5 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
* Program counter (PC) .............................................................. Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)
INT0 pin (LH or HL input) INT1 pin (LH or HL input)
EXF0
V10
Address 0 in page 1 Address 2 in page 1
EXF1
V11
Timer 1 underflow
T1F
V12
Address 4 in page 1
Main rouine Interrupt service routine
Interrupt occurs
Timer 2 underflow
T2F
V13
Address 6 in page 1
Timer 3 underflow
T3F
V20
Address 8 in page 1
* * * *
Timer 4 underflow
T4F
V21
Address A in page 1
EI RTI
Interrupt is enabled
Completion of A-D conversion
ADF
V22
Address C in page 1
Completion of serial I/O transfer Activated condition
SIOF Request flag (state retained)
V23 Enable bit
INTE
Address E in page 1
Enable flag
Fig. 15 Interrupt system diagram
: Interrupt enabled state : Interrupt disabled state
Fig. 13 Program example of interrupt processing
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Interrupt control registers
* Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
* Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid)
Note: "R" represents read enabled, and "W" represents write enabled.
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10-V13 and V20-V23), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc-
curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
When an interrupt request flag is set after its interrupt is enabled (Note 1)
f (XIN) (middle-speed mode)
f (XIN) (high-speed mode)
1 machine cycle
T1 System clock
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
Interrupt enable flag (INTE)
EI instruction execution cycle Interrupt enabled state
Interrupt disabled state
INT0, INT1 External interrupt EXF0, EXF1 Interrupt activated condition is satisfied. T1F, T2F, T3F, T4F, ADF,SIOF
Retaining level of system clock for 4 periods or more is necessary.
Timer 1, Timer 2, Timer 3, Timer 4, A-D, and Serial I/O interrupts
Flag cleared 2 to 3 machine cycles (Notes 2, 3)
The program starts from the interrupt address.
Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset. 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
EXTERNAL INTERRUPTS
The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin P30/INT0 Activated condition When the next waveform is input to P30/INT0 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms External 1 interrupt P31/INT1 When the next waveform is input to P31/INT1 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms I21 I22 Valid waveform selection bit I11 I12
I12 Falling
0
One-sided edge detection circuit
I11
0
P30/INT0
1 1
EXF0 Both edges detection circuit Wakeup Skip SNZI0
External 0 interrupt
Rising
I22 Falling
0
One-sided edge detection circuit
I21
0
P31/INT1
1 1
EXF1 Both edges detection circuit Wakeup Skip SNZI1
External 1 interrupt
Rising
Fig. 17 External interrupt circuit structure
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P30/INT0 pin need not be selected the external interrupt input INT0 function or the normal I/O port P30 function. However, the EXF0 flag is set to "1" when a valid waveform is input even if it is used as an I/O port P30. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to "1" when a valid waveform is input to P31/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P31/INT1 pin need not be selected the external interrupt input INT1 function or the normal I/O port P31 function. However, the EXF1 flag is set to "1" when a valid waveform is input even if it is used as an I/O port P31. * External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. Select the valid waveform with the bits 1 and 2 of register I2. Clear the EXF1 flag to "0" with the SNZ1 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. Set both the external 1 interrupt enable bit (V11) and the INTE flag to "1." The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to "1" and the external 1 interrupt occurs.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(3) External interrupt control registers
* Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.
* Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 8 External interrupt control registers Interrupt control register I1 I13 Not used 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 at RAM back-up : state retained R/W
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit Interrupt control register I2
I23
Not used
0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TIMERS
The 4513/4514 Group has the programmable timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
* Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse.
FF16 n : Counter initial value Count starts n
The contents of counter
Reload
Reload
1st underflow
2nd underflow
0016 Time n+1 count "1" Timer interrupt "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 18 Auto-reload function
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
The 4513/4514 Group timer consists of the following circuits. * Prescaler : frequency divider * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 8-bit programmable timer * Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively) * 16-bit timer Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below. Table 9 Function related timers Circuit Prescaler Timer 1 Structure Frequency divider 8-bit programmable binary down counter (link to EXF0) Timer 2 8-bit programmable binary down counter * Timer 1 underflow * Prescaler output (ORCLK) * CNTR0 input * 16-bit counter underflow Timer 3 8-bit programmable binary down counter (link to EXF1) Timer 4 8-bit programmable binary down counter 16-bit timer 16-bit fixed dividing frequency * Timer 3 underflow * Prescaler output (ORCLK) * CNTR1 input * Instruction clock 65536 * Watchdog timer (The 15th bit is counted twice) * Timer 2 count source (16-bit counter underflow) 1 to 256 * Timer 2 underflow * Prescaler output (ORCLK) 1 to 256 * Timer 4 count source * Timer 3 interrupt * CNTR1 output * Timer 4 interrupt * CNTR1 output W3 W6 W4 W6 1 to 256 Count source * Instruction clock * Prescaler output (ORCLK) Frequency dividing ratio 4, 16 1 to 256 Use of output signal * Timer 1, 2, 3 and 4 count sources * Timer 2 count source * CNTR0 output * Timer 1 interrupt * Timer 3 count source * Timer 2 interrupt * CNTR0 output W2 W6 Control register W1 W1 W6
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Instruction clock
W13
Prescaler
W12 1/4 1/16
0 1
Division circuit (divided by 2)
XIN
MR3
1 0
0
Internal clock generation circuit (divided by 3)
I12 P30/INT0
0 1
1
ORCLK W10 SQ I10 R
1 0
W11 (Note)
0 1
Timer 1 (8) Reload register R1 (8)
T1AB (TR1AB) T1AB
T1F
Timer 1 interrupt
(TAB1)
Register B Register A Timer 1 underflow signal
W21,W20
00 01 10 11 0 1
W23(Note)
Timer 2 (8) Reload register R2 (8)
(T2AB)
T2F
Timer 2 interrupt
(TAB2)
Register B Register A Timer 2 underflow signal
W32 SQ I20 R
1 0
I22 P31/INT1
0 1
W31,W30
00 01 10 11
Not available Not available
W33(Note)
0 1
Timer 3 (8) Reload register R3 (8)
T3AB (TR3AB) T3AB
T3F
Timer 3 interrupt
(TAB3)
Register B Register A Timer 3 underflow signal
W41,W40
00 01 10 11
Not available
W43(Note)
0 1
Timer 4 (8) Reload register R4 (8)
(T4AB)
T4F
Timer 4 interrupt
(TAB4)
Register B Register A
W60 D6/CNTR0
0 1
D6 output
W61
0 1
1/2 1/2 Timer 2 underflow signal 1/2 1/2 Timer 4 underflow signal
W62 D7/CNTR1
0 1
D7 output
W63
0 1
Data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (autoreload function) Note: Count source is stopped by clearing to "0."
Instruction clock
16-bit timer (WDT)
1 - - - - - - - - - - - 15 16
System reset
WRST instruction S
WEF
Reset signal
R
Q
WDF1 WDF2
Fig. 19 Timers structure
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Table 10 Timer control registers Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Not used 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected at reset : 00002 at RAM back-up : state retained R/W
0 Stop (state retained) 1 Operating 0 This bit has no function, but read/write is enabled. 1 W21 W20 Count source 0 0 1 1 0 1 0 1 Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal at RAM back-up : state retained R/W
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits W30 Timer 3 control bit Timer 3 count start synchronous circuit control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Count source Timer 2 underflow signal Prescaler output Not available Not available at RAM back-up : state retained R/W
Timer control register W4 W43 W42 W41 Timer 4 count source selection bits W40 Timer 4 control bit Not used
at reset : 00002 0 1 0 1 W41 W40 0 0 0 1 1 0 1 1
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available at RAM back-up : state retained R/W
Timer control register W6 W63 W62 W61 W60 CNTR1 output control bit D7/CNTR1 function selection bit CNTR0 output control bit D6/CNTR0 output control bit 0 1 0 1 0 1 0 1
at reset : 00002
Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input)
Note: "R" represents read enabled, and "W" represents write enabled.
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(1) Timer control registers
* Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. * Timer control register W6 Register W6 controls the D6/CNTR0 pin and D7/CNTR1 functions, the selection and operation of the CNTR0 and CNTR1 output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to "0."
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process; set data in timer 1, and set the bit 1 of register W1 to "1." However, P30/INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to "1." Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction. Timer 1 underflow signal divided by 2 can be output from D6/CNTR0 pin.
(2) Precautions
Note the following for the use of timers. * Prescaler Stop the prescaler operation to change its frequency dividing ratio. * Count source Stop timer 1, 2, 3, or 4 counting to change its count source. * Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. * Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows.
(5) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register W2, and set the bit 3 of register W2 to "1." Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2, and count continues (auto-reload function). When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction. The output from D6/CNTR0 pin by timer 2 underflow signal divided by 2 can be controlled.
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(6) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. When writing data to reload register R3 with the TR3AB instruction, the downcount after the underflow is started from the setting value of reload register R3. Timer 3 starts counting after the following process; set data in timer 3, select the count source with the bits 0 and 1 of register W3, and set the bit 3 of register W3 to "1." However, P31/INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 2 of register W3 to "1." Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes "0"), the timer 3 interrupt request flag (T3F) is set to "1," new data is loaded from reload register R3, and count continues (auto-reload function). When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 3 with the TAB3 instruction. When reading the data, stop the counter and then execute the TAB3 instruction. Timer 3 underflow signal divided by 2 can be output from D7/CNTR1 pin.
(8) Timer I/O pin (D6/CNTR0, D7/CNTR1)
D6/CNTR0 pin has functions to input the timer 2 count source, and to output the timer 1 and timer 2 underflow signals divided by 2. D7/CNTR1 pin has functions to input the timer 4 count source, and to output the timer 3 and timer 4 underflow signals divided by 2. The selection of D6/CNTR0 pin function can be controlled with the bit 0 of register W6. The selection of D7/CNTR1 pin function can be controlled with the bit 2 of register W6. The following signals can be selected for the CNTR0 output signal with the bit 1 of register W6. * timer 1 underflow signal divided by 2 * the signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divide by 2 The following signals can be selected for the CNTR1 output signal with the bit 3 of register W6. * timer 3 underflow signal divided by 2 * the signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divide by 2 Timer 2 counts the rising waveform of CNTR0 input when the CNTR0 input is selected as the count source. Timer 4 counts the rising waveform of CNTR1 input when the CNTR1 input is selected as the count source.
(9) Timer interrupt request flags (T1F, T2F, T3F, and T4F)
Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, and SNZT4). Use the interrupt control registers V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction.
(7) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with the timer 4 reload register (R4). Data can be set simultaneously in timer 4 and the reload register (R4) with the T4AB instruction. Timer 4 starts counting after the following process; set data in timer 4, select the count source with the bits 0 and 1 of register W4, and set the bit 3 of register W4 to "1." Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes "0"), the timer 4 interrupt request flag (T4F) is set to "1," new data is loaded from reload register R4, and count continues (auto-reload function). When a value set in reload register R4 is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 4 with the TAB4 instruction. When reading the data, stop the counter and then execute the TAB4 instruction. The output from D7/CNTR1 pin by timer 4 underflow signal divided by 2 can be controlled.
(10) Count start synchronization circuit (timer 1, timer 3)
Each timer 1 and timer 3 has the count start synchronization circuit which synchronize P30/INT0 pin and P31/INT1 pin, respectively, and can start the timer count operation. Timer 1 count start synchronization circuit function is selected by setting the bit 0 of register W1 to "1." The control by P30/INT0 pin input can be performed by setting the bit 0 of register I1 to "1." P30/INT0 pin input level can be selected by the bit 2 of register I1 as follows; * I12 = "0": The count start synchronizes the "L" level of P30/INT0 pin * I12 = "1": The count start synchronizes the "H" level of P30/INT0 pin Timer 3 count start synchronization circuit function is selected by setting the bit 2 of register W3 to "1." The control by P31/INT1 pin input can be performed by setting the bit 0 of register I2 to "1." P31/INT1 pin input level can be selected by the bit 2 of register I2 as follows; * I22 = "0": The count start synchronizes the "L" level of P31/INT1 pin * I22 = "1": The count start synchronizes the "H" level of P31/INT1 pin When timer 1 and timer 3 count start synchronization circuits are used, the count start synchronization circuits are set, the count source is input to each timer by inputting valid levels to P30/INT0 pin and P31/INT1 pin. Once set, the count start synchronization circuit is cleared by clearing the bit I10 or I20 to "0" or reset.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source. The underflow signal is generated when the count value reaches "000016." This underflow signal can be used as the timer 2 count source. When the WRST instruction is executed after system is released from reset, the WEF flag is set to "1". At this time, the watchdog timer starts operating.
When the count value of timer WDT reaches "BFFF16" or "3FFF16," the WDF1 flag is set to "1." If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. To prevent the WDT stopping in the event of misoperation, WEF flag is designed not to initialize once the WRST instruction has been executed. Note also that, if the WRST instruction is never executed, the watchdog timer does not start.
FFFF16
The value of timer (WDT)
0000 16
WEF flag
BFFF16 3FFF16
WDF1 flag WDF2 flag
RESET pin output WRST instruction executed
Fig. 20 Watchdog timer function The contents of WEF, WDF1 and WDF2 flags and timer WDT are initialized at the RAM back-up mode. If WDF2 flag is set to "1" at the same time that the microcomputer enters the RAM back-up state, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 21)
WRST instruction executed
System reset
* * * * * * WRST EPOF POF
; WDF1 flag reset ; POF instruction enabled
Oscillation stop
(RAM back-up state)
Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SERIAL I/O
The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; * serial I/O register SI * serial I/O mode register J1 * serial I/O transmission/reception completion flag (SIOF) * serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1.
Table 11 Serial I/O pins Pin P20/SCK P21/SOUT P22/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN)
Note: Input ports P20-P22 can be used regardless of register J1.
Division circuit (divided by 2) XIN
MR3
1 0
Internal clock generation circuit (divided by 3)
Instruction clock
J12 1/4 1/8
1 0
Serial I/O mode register J1 J13 J12 J11 J10
P20/SCK
SCK
Synchronous circuit
Serial I/O counter (3)
SIOF
Serial I/O interrupt
P21/SOUT
SOUT
P22/SIN
SIN
MSB
Serial I/O register SI (8) TSIAB
LSB TABSI
J11
J10
Register B (4)
Register A (4)
Note: The output structure of SCK and SOUT pins is N-channel open-drain.
Fig. 22 Serial I/O structure Table 12 Serial I/O mode register Serial I/O mode register J1 J13 J12 J11 J10 Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit Serial I/O synchronous clock selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8)
Note: "R" represents read enabled, and "W" represents write enabled.
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When transmitting (D7-D0 : transfer data)
SIN pin
When receiving
SOUT pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
SOUT pin
SIN pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
Transfer data to be set
D0
D7 D6 D5 D4 D3 D2 D1
Transfer started

D7 D6 D5 D4 D3 D2
D1 D0
Fig. 23 Serial I/O register state when transferring
Transfer completed
D7 D6 D5 D4 D3 D2 D1 D0
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, pull up the SCK pin or set the pin function to an input port P20.
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to "0" and then serial I/O transmission/reception is started.
(4) Serial I/O mode register J1
Register J1 controls the synchronous clock, P20/SCK, P21/SOUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A.
(2) Serial I/O transmission/reception completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to "1" when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
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(5) How to use serial I/O
Figure 24 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the
wiring between each pin with a resistor. Figure 25 shows the data transfer timing and Table 13 shows the data transfer sequence.
Master (clock control)
Slave (external clock)
D5 SCK SOUT SIN
SRDY signal
D5 SCK SIN SOUT
(Bit 3) ! ! 1
(Bit 0) 1 Serial I/O mode register J1 Internal clock selected as a synchronous clock Serial I/O port SCK,SOUT,SIN Instruction clock divided by 8 or 4 selected as a transfer clock
(Bit 3) !
!
1
(Bit 0) 0 Serial I/O mode register J1 External clock selected as a synchronous clock Serial I/O port SCK,SOUT,SIN This bit is not valid when J10="0"
(Bit 3) 0 !
!
(Bit 0) Interrupt control register V2 !
(Bit 3) 0
!
!
(Bit 0) ! Interrupt control register V2
Serial I/O interrupt enable bit (SNZSI instruction is valid)
Serial I/O interrupt enable bit (SNZSI instruction is valid)
! : Set an arbitrary value.
Fig. 24 Serial I/O connection example
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Master
SOUT SIN SST instruction
M7' S7'
M0 S0
M1 S1
M2 S2
M3 S3
M4 S4
M5 S5
M6 S6
M7 S7
SCK
Slave
SST instruction SRDY signal
SOUT SIN
S7' M7'
S0 M0
S1 M1
S2 M2
S3 M3
S4 M4
S5 M5
S6 M6
S7 M7
M0-M7 : the contents of master serial I/O S0-S7 : the contents of slave serial I/O register Rising of SCK : serial input Falling of SCK : serial output
Fig. 25 Timing of serial I/O data transfer
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Table 13 Processing sequence of data transfer from master to slave Master (transmission) [Initial setting] * Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions * Setting the port received the reception enable signal (SRDY) to the input mode. (Port D5 is used in this example) SD instruction * [Transmission enable state] * Storing transmission data to serial I/O register SI. TSIAB instruction Slave (reception) [Initial setting] * Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions * Setting the port received the reception enable signal (SRDY) and outputting "H" level (reception impossible). (Port D5 is used in this example) SD instruction *[Reception enable state] * The SIOF flag is cleared to "0." SST instruction * "L" level (reception possible) is output from port D5. RD instruction [Reception]
[Transmission] *Check port D5 is "L" level. SZD instruction *Serial transfer starts. SST instruction *Check transmission completes. SNZSI instruction *Wait (timing when continuously transferring)
* Check reception completes. SNZSI instruction * "H" level is output from port D5. SD instruction [Data processing]
1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to "1" when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to "H."
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. Table 14 shows the characteristics of this A-D converter. This AD converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Table 14 A-D converter characteristics Characteristics Parameter Successive comparison method Conversion format Resolution Absolute accuracy Conversion speed Analog input pin 10 bits Linearity error: 2LSB Non-linearity error: 0.9LSB 46.5 s (High-speed mode at 4.0 MHz oscillation frequency) 4 for 4513 Group 8 for 4514 Group
Register B (4)
Register A (4) 4 TAQ2 TQ2A
Q23 Q22 Q21 Q20
4 4
IAP4 (P40--P43)
TAQ1 TQ1A 2
Q13 Q12 Q11 Q10
4
8 TABAD
8 TADAB
TALA Instruction clock 1/6
OP4A (P40--P43) 3
Q23
0
8-channel multi-plexed analog switch
(Note 3) AIN0/CMP0AIN1/CMP0+ AIN2/CMP1AIN3/CMP1+ P40/AIN8 P41/AIN9 P42/AIN10 P43/AIN11
A-D control circuit
1
ADF (1)
A-D interrupt
1
Comparator
0
Successive comparison register (AD) (10) 10 10
1
Q23 8
0 1 0
Q23
1
DAC operation signal
Q23
8 DA converter (Note 1) VSS Comparator register (8) (Note 2) VDD 8 8
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1). The value of the comparator register is retained even when the mode is switched to the A-D conversion mode (Q23=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. 3: The 4513 Group does not have ports P40/AIN4-P43/AIN7 and the IAP4 and OP4A instructions.
Fig. 26 A-D conversion circuit structure
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Table 15 A-D control registers
A-D control register Q1 Q13 Not used at reset : 00002 0 1 Q12Q11 Q10 000 001 010 011 100 101 110 111 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at RAM back-up : state retained R/W
Q12
Q11
Analog input pin selection bits (Note 2)
Q10
A-D control register Q2 Q23 Q22 Q21 Q20 A-D operation mode selection bit P43/AIN7 and P42/AIN6 pin function selection bit (Not used for the 4513 Group) P41/AIN5 pin function selection bit (Not used for the 4513 Group) P40/AIN4 pin function selection bit (Not used for the 4513 Group) 0 1 0 1 0 1 0 1
at reset : 00002 A-D conversion mode
Comparator mode (read/write enabled for the 4513 Group) P43, P42 AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 AIN5/P41 P40 AIN4/P40 (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2.
(1) Operating at A-D conversion mode
The A-D conversion mode is set by setting the bit 3 of register Q2 to "0."
(4) A-D conversion start instruction (ADST)
A-D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD.
(2) Successive comparison register AD
Register AD stores the A-D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute this instruction during AD conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref =
(5) A-D control register Q1
Register Q1 is used to select one of analog input pins. The 4513 Group does not have AIN4-AIN7. Accordingly, do not select these pins with register Q1.
(6) A-D control register Q2
Register Q2 is used to select the pin function of P40/AIN4, P41/ AIN5, P42/AIN6, and P43/AIN7. The A-D conversion mode is selected when the bit 3 of register Q2 is "0," and the comparator mode is selected when the bit 3 of register Q2 is "1." After set this register, select the analog input with register Q1. Even when register Q2 is used to set the pins for analog input, P40/AIN4-P43/AIN7 continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, for the port input, the port input function of the pin functions as analog input is undefined.
VDD !n 1024
n: The value of register AD (n = 0 to 1023)
(3) A-D conversion completion flag (ADF)
A-D conversion completion flag (ADF) is set to "1" when A-D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Operation description
A-D conversion is started with the A-D conversion start instruction (ADST). The internal operation during A-D conversion is as follows: When A-D conversion starts, the register AD is cleared to "00016." Next, the topmost bit of the register AD is set to "1," and the comparison voltage Vref is compared with the analog input voltage VIN. When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to "1." When the comparison result is Vref > VIN, it is cleared to "0."
The 4513/4514 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A-D conversion stops after 62 machine cycles (46.5 s when f(XIN) = 4.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A-D interrupt activated condition is satisfied and the ADF flag is set to "1" as soon as A-D conversion completes (Figure 27).
Table 16 Change of successive comparison register AD during A-D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes U1: 1st comparison result U3: 3rd comparison result U9: 9th comparison result Change of successive comparison register AD
-------------
Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD 4

1 U1 U1
0 1 U2
0 0 1
-------------
0 0 0
0 0 0
0 0 0
-------------------------------------------------------------

VDD 8 VDD 1024
A-D conversion result
-------------
U1
U2
U3
-------------
-----
U8
U9
UA
2
U2: 2nd comparison result U8: 8th comparison result UA: Ath comparison result
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(8) A-D conversion timing chart
Figure 27 shows the A-D conversion timing chart.
ADST instruction 62 machine cycles A-D conversion completion flag (ADF) DAC operation signal
Fig. 27 A-D conversion timing chart
(9) How to use A-D conversion
How to use A-D conversion is explained using as example in which the analog input from P40/AIN4 pin is A-D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A-D interrupt is not used in this example. After selecting the AIN4 pin function with the bit 0 of the register Q2, select AIN4 pin and A-D conversion mode with the register Q1 (refer to Figure 28). Execute the ADST instruction and start A-D conversion. Examine the state of ADF flag with the SNZAD instruction to determine the end of A-D conversion. Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
0
!
!
1
A-D control register Q2 AIN4 function selected A-D conversion mode
(Bit 3)
(Bit 0)
!
1
0
0
A-D control register Q1
AIN4 pin selected
! : Set an arbitrary value
Fig. 28 Setting registers
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(10) Operation at comparator mode
The A-D converter is set to comparator mode by setting bit 3 of the register Q2 to "1." Below, the operation at comparator mode is described.
(12) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A-D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
(11) Comparator register
In comparator mode, the built-in DA comparator is connected to the comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A-D conversion mode to comparator mode, the result of A-D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A-D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 !n
(13) Comparator operation start instruction (ADST instruction)
In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (6 s at f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1."
(14) Notes for the use of A-D conversion 1
Note the following when using the analog input pins also for I/O port P4 functions: * Even when P40/AIN4-P43/AIN7 are set to pins for analog input, they continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
n: The value of register AD (n = 0 to 255)
ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal
Comparator operation completed. (The value of ADF is determined)
Fig. 29 Comparator operation timing chart
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(15) Notes for the use of A-D conversion 2
Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with bit 3 of register Q2 while A-D converter is operating. When the operating mode of A-D converter is changed from the comparator mode to A-D conversion mode with the bit 3 of register Q2, note the following; * Clear bit 2 of register V2 to "0" to change the operating mode of the A-D converter from the comparator mode to A-D conversion mode with the bit 3 of register Q2. * The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag.
(16) Definition of A-D converter accuracy
The A-D conversion accuracy is defined below (refer to Figure 30). * Relative accuracy Zero transition voltage (V0T) This means an analog input voltage when the actual A-D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A-D conversion output data changes from "1023" to "1022." Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. * Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A-D conversion characteristics.
Output data
1023 1022
Full-scale transition voltage (VFST)
Differential non-linearity error = b-a [LSB] a Linearity error = c [LSB] a
b a
n+1 n
Actual A-D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1-Vn c: Difference between ideal Vn and actual Vn
Ideal line of A-D conversion between V0-V1022
1 0
V0
V1
Vn
Vn+1
V1022 Analog voltage
VDD
Zero transition voltage (V0T)
Fig. 30 Definition of A-D conversion accuracy Vn: Analog input voltage when the output data changes from "n" to "n+1" (n = 0 to 1022) * 1LSB at relative accuracy VFST-V0T (V) 1022 VDD 1024
* 1LSB at absolute accuracy
(V)
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE COMPARATOR
The 4513/4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins. Table 17 shows the characteristics of this voltage comparison.
Table 17 Voltage comparator characteristics Characteristics Parameter Voltage comparator function 2 circuits (CMP0, CMP1) Input pin CMP0-, CMP0+ (also used as AIN0, AIN1) CMP1-, CMP1+ Supply voltage Input voltage Comparison check error Response time (also used as AIN2, AIN3) 3.0 V to 5.5 V 0.3 VDD to 0.7 VDD Typ. 20 mV, Max.100 mV Max. 20 s
CMP0-/AIN0 CMP0+/AIN1
- CMP0 +
CMP1-/AIN2 CMP1+/AIN3
- CMP1 +
Q33 Q32 Q31 Q30 Voltage comparator control register Q3 (4) TQ3A TAQ3 Register A (4) Note: Bits 0 and 1 of register Q3 can be only read.
Fig. 31 Voltage comparator structure
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Table 18 Voltage comparator control register Q3
Voltage comparator control register Q3 (Note 2) Q33 Q32 Q31 Q30 Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit CMP1 comparison result store bit CMP0 comparison result store bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
Voltage comparator (CMP1) invalid Voltage comparator (CMP1) valid Voltage comparator (CMP0) invalid Voltage comparator (CMP0) valid CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Bits 0 and 1 of register Q3 can be only read.
(1) Voltage comparator control register Q3
Register Q3 controls the function of the voltage comparator. The function of the voltage comparator CMP0 becomes valid by setting bit 2 of register Q3 to "1," and becomes invalid by setting bit 2 of register Q3 to "0." The comparison result of the voltage comparator CMP0 is stored into bit 0 of register Q3. The function of the voltage comparator CMP1 becomes valid by setting bit 3 of register Q3 to "1," and becomes invalid by setting bit 3 of register Q3 to "0." The comparison result of the voltage comparator CMP1 is stored into bit 1 of register Q3.
(3) Precautions
When the voltage comparator is used, note the following; * Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = "0") the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator by software when it is unused. * Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. * Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function becomes valid.
(2) Operation description of voltage comparator
The voltage comparator function becomes valid by setting each control bit of register Q3 to "1" and compares the voltage of the input pin. The comparison result is stored into each comparison result store bit of register Q3. The comparison result is as follows; * When CMP0- > CMP0+, Q30 = "0" When CMP0- < CMP0+, Q30 = "1" * When CMP1- > CMP1+, Q31 = "0" When CMP1- < CMP1+, Q31 = "1"
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RESET FUNCTION
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when "H" level is applied to RESET pin, software starts from address 0 in page 0.
f(XIN)
RESET
(Note) f(XIN) is counted 16892 to
16895 times.
Software starts (address 0 in page 0)
Note: It depends on the internal state of the microcomputer when reset is performed.
Fig. 32 Reset release timing
Reset input
=
1 machine cycle or more
f(XIN) is counted 16892 to 16895 times.
0.85VDD RESET 0.3VDD
Software starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 33 RESET pin input waveform and reset operation
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Power-on reset
Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance.
VDD
VDD RESET pin voltage
Internal reset signal
RESET pin
(Note)
Reset state
Voltage drop detection circuit
Watchdog timer output
WEF
Internal reset signal
Reset released Note: Power-on This symbol represents a parasitic diode. Applied potential to RESET pin must be VDD or less.
Fig. 34 Power-on reset circuit example
(2) Internal state at reset
Table 19 shows port state at reset, and Figure 35 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 35 are undefined, so set the initial value to them. Table 19 Port state at reset Name D0-D5 D6/CNTR0, D7/CNTR1 P00-P03 P10-P13 P20/SCK, P21/SOUT, P22/SIN P30/INT0, P31/INT1 P32, P33 (Note 4) P40/AIN4-P43/AIN7 (Note 4) P50-P53 (Note 4) D0-D5 D6, D7 P00-P03 P10-P13 P20-P22 P30, P31 P32, P33 P40-P43 P50-P53 High impedance High impedance (Note 1) High impedance (Note 1) High impedance (Note 3) High impedance (Notes 1, 2) Function High impedance (Note) State
Notes 1: Output latch is set to "1." 2: Pull-up transistor is turned OFF. 3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 00002) 4: The 4513 Group does not have these ports.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
* Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) .................................................................................................. 0 * Power down flag (P) ............................................................................................................. 0 * External 0 interrupt request flag (EXF0) .............................................................................. 0 * External 1 interrupt request flag (EXF1) .............................................................................. 0 * Interrupt control register V1 .................................................................................................. 0 000 * Interrupt control register V2 .................................................................................................. 0 000 * Interrupt control register I1 ................................................................................................... 0 000 * Interrupt control register I2 ................................................................................................... 0 000 * Timer 1 interrupt request flag (T1F) ..................................................................................... 0 * Timer 2 interrupt request flag (T2F) ..................................................................................... 0 * Timer 3 interrupt request flag (T3F) ..................................................................................... 0 * Timer 4 interrupt request flag (T4F) ..................................................................................... 0 * Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 * Watchdog timer enable flag (WEF) ...................................................................................... 0 * Timer control register W1 ..................................................................................................... 0 000 * Timer control register W2 ..................................................................................................... 0 000 * Timer control register W3 ..................................................................................................... 0 000 * Timer control register W4 ..................................................................................................... 0 000 * Timer control register W6 ..................................................................................................... 0 000 * Clock control register MR ..................................................................................................... 0 100 * Serial I/O transmission/reception completion flag (SIOF) ................................................... 0 * Serial I/O mode register J1 .................................................................................................. 0 000 !!!!!!! * Serial I/O register SI ............................................................................................................. ! * A-D conversion completion flag (ADF) ................................................................................. 0 * A-D control register Q1 ......................................................................................................... 0 000 * A-D control register Q2 ......................................................................................................... 0 000 * Voltage comparator control register Q3 ............................................................................... 0 000 !!!!!!!!! * Successive comparison register AD .................................................................................... ! ! ! ! ! ! ! ... * Comparator register ...........................................................................................................! ! * Key-on wakeup control register K0 ...................................................................................... 0 000 * Pull-up control register PU0 ................................................................................................. 0 000 * Direction register FR0 .......................................................................................................... 0 000 * Carry flag (CY) ...................................................................................................................... 0 * Register A ............................................................................................................................. 0 000 * Register B ............................................................................................................................. 0 000 * Register D ............................................................................................................................. ! !! !!!!!!! * Register E ............................................................................................................................. ! * Register X ............................................................................................................................. 0 000 * Register Y ............................................................................................................................. 0 000 * Register Z ............................................................................................................................. ! ! * Stack pointer (SP) ................................................................................................................ 1 11
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler and timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped)
(External clock selected and serial I/O port not selected)
(Port P5: input mode)
"!" represents undefined. Fig. 35 Internal state at reset
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
RESET pin
Internal reset signal Voltage drop detection circuit Watchdog timer output WEF Note: The output structure of RESET pin is N-channel open-drain.
Fig. 36 Voltage drop detection reset circuit
VDD VRST (detection voltage)
Voltage drop detection circuit output The microcomputer starts operation after f(XIN) is counted 16892 to 16895 times. RESET pin Notes 1: Pull-up RESET pin externally. 2: Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST (detection voltage).
Fig. 37 Voltage drop detection circuit operation waveform
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 20 shows the function and states retained at RAM back-up. Figure 38 shows the state transition.
Table 20 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Timer control register W1 Timer control registers W2 to W4, W6 Clock control register MR Interrupt control registers V1, V2 Interrupt control registers I1, I2 Timer 1 function Timer 2 function Timer 3 function Timer 4 function A-D conversion function A-D control registers Q1, Q2 Voltage comparator function Voltage comparator control register Q3 Serial I/O function Serial I/O mode register J1 Pull-up control register PU0 Key-on wakeup control register K0 Direction register FR0 External 0 interrupt request flag (EXF0) External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Timer 4 interrupt request flag (T4F) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) 16-bit timer (WDT) A-D conversion completion flag (ADF) Serial I/O transmission/reception completion flag (SIOF) Interrupt enable flag (INTE) RAM back-up ! O O ! O ! ! O ! (Note 3) (Note 3) (Note 3) ! O O (Note 5) O ! O O O O ! ! ! (Note 3) (Note 3) (Note 3) ! (Note 4) ! (Note 4) ! (Note 4) ! ! !
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is "1."
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0 when; * reset pulse is input to RESET pin, or * reset by watchdog timer is performed, or * voltage drop detection circuit detects the voltage drop. In this case, the P flag is "0."
Notes 1:"O" represents that the function can be retained, and "!" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The state is retained when the voltage comparator function is selected with the voltage comparator control register Q3.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Return signal
An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 21 shows the return condition for each return source.
(5) Ports P0 and P1 control registers
* Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
External wakeup signal
Table 21 Return source and return condition Return condition Return source Return by an external falling Ports P0, P1 edge input ("H""L"). Port P30/INT0 Return by an external "H" level or "L" level input. The EXF0 flag is not set. Return by an external "H" level or "L" level input. The EXF1 flag is not set.
Remarks Set the port using the key-on wakeup function selected with register K0 to "H" level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Select the return level ("L" level or "H" level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state. Select the return level ("L" level or "H" level) with the bit 2 of register I2 according to the external state before going into the RAM back-up state.
Port P31/INT1
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A (Stabilizing time a ) Reset f(XIN) oscillation
POF instruction is executed Return input (Stabilizing time a )
B f(XIN) stop (RAM back-up mode)
Stabilizing time a : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware.
Fig. 38 State transition
Power down flag P POF instruction Reset input or voltage drop detection circuit output S Q
Software start P = "1" ? No Cold start Yes
R
q Set source * * * * * * * POF instruction is executed q Clear source * * * * * * Reset input
Warm start
Fig. 39 Set source and clear source of the P flag
Fig. 40 Start condition identified example using the SNZP instruction
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and P13 pull-up transistor control bit Pins P10 and P11 pull-up transistor control bit Pins P02 and P03 pull-up transistor control bit Pins P00 and P01 pull-up transistor control bit Interrupt control register I1 I13 Not used 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 at RAM back-up : state retained R/W at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 at RAM back-up : state retained R/W
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit Interrupt control register I2
I23
Not used
0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CLOCK CONTROL
The clock control circuit consists of the following circuits. * System clock generating circuit * Control circuit to stop the clock oscillation
* Control circuit to switch the middle-speed mode and high-speed mode * Control circuit to return from the RAM back-up state
Division circuit (divided by 2) XIN XOUT
MR3
1 0
System clock Internal clock generation circuit (divided by 3) Instruction clock Counter Wait time (Note) control circuit
Oscillation circuit
POF instruction
R S
Q
RESET Key-on wake up control register K00,K01,K02,K03 Ports P00, P01 MultiPorts P02, P03 Falling detected Ports P10, P11 plexer Ports P12, P13 I12
"L" level
Software start signal
0
P30/INT0
1
"H" level
I22
"L" level
0
P31/INT1
1
"H" level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 41 Clock control circuit structure Table 23 Clock control register MR Clock control register MR MR3 MR2 MR1 MR0 System clock selection bit Not used Not used Not used 0 1 0 1 0 1 0 1 at reset : 10002 f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. at RAM back-up : 10002 R/W
Note : "R" represents read enabled, and "W" represents write enabled.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. When an external clock signal is input, connect the clock source to XIN and leave XOUT open. When using an external clock, the maximum value of external clock oscillating frequency is shown in Table 24.
4513/4514
XIN
CIN
Note: Externally connect a damping resistor Rd depending on the oscillation XOUT frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer's recommended value because constants COUT such as capacitance depend on the resonator.
Fig. 42 Ceramic resonator external circuit
4513/4514
XIN
XOUT
VDD VSS
External oscillation circuit
Fig. 43 External clock input circuit
Table 24 Maximum value of external clock oscillation frequency Middle-speed mode Mask ROM version High-speed mode Middle-speed mode One Time PROM version High-speed mode Supply voltage VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V Oscillation frequency (duty ratio) 3.0 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 1.0 MHz (40 % to 60 %) 0.8 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 3.0 MHz (40 % to 60 %) 1.0 MHz (40 % to 60 %)
ROM ORDERING METHOD
Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form ..................................... 1 (2) Data to be written into mask ROM ............................... EPROM (three sets containing the identical data) (3) Mark Specification Form .......................................................... 1
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k in series at the shortest distance. Prescaler Stop the prescaler operation to change its frequency dividing ratio. Timer count source Stop timer 1, 2, 3, or 4 counting to change its count source. Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. P30/INT0 pin When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Clear the bit 0 of register V1 to "0" before the interrupt valid waveform of P30/INT0 pin is changed with the bit 2 of register I1 (refer to Figure 44). * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 44)
P31/INT1 pin When the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Clear the bit 1 of register V1 to "0" before the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 (refer to Figure 45). * Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I2 and execute the SNZ1 instruction to clear the EXF1 flag after executing at least one instruction (refer to Figure 45).
. . .
LA 8 TV1A LA 8 TI2A NOP SNZ1 NOP ; (!!0!2) ; The SNZ1 instruction is valid ........... ; Change of the interrupt valid waveform ........................................................... ; The SNZ1 instruction is executed
. . .
! : this bit is not related to the setting of INT1.
Fig. 45 External 1 interrupt program example One Time PROM version The operating power voltage of the One Time PROM version is 2.5 V to 5.5 V. Multifunction The input of D6, D7, P20-P22, I/O of P30 and P31, input of CMP0-, CMP0+, CMP1-, CMP1+, and I/O of P40-P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, AIN0-AIN3 and AIN4-AIN7 are selected.
. . .
LA 4 TV1A LA 4 TI1A NOP SNZ0 NOP ; (!!!02) ; The SNZ0 instruction is valid ........... ; ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed
. . .
! : this bit is not related to the setting of INT0 pin. Fig. 44 External 0 interrupt program example
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. * Clear the bit 2 of register V2 to "0" to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46). * The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with the bit 3 of register Q2 during operating the A-D converter.
Sensor
AIN
Apply the voltage withiin the specifications to an analog input pin.
Fig. 47 Analog input external circuit example-1
. . .
LA 8 TV2A LA 0 TQ2A ; (!0!!2) ; The SNZAD instruction is valid ........ ; (0!!!2) ; Change of the operating mode of the A-D converter from the comparator mode to the A-D conversion mode
About 1k
Sensor
AIN
SNZAD NOP
Fig. 48 Analog input external circuit example-2 !: this bit is not related to the change of the operating mode of the A-D conversion.
12
. . .
Fig. 46 A-D converter operating mode program example
11
A-D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins (Figure 47). When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48. In addition, test the application products sufficiently.
POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Analog input pins Note the following when using the analog input pins also for I/O port P4 functions: * Even when P40/AIN4-P43/AIN7 are set to pins for analog input, they continue to function as P40-P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
13 14
Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined.
15
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
16
Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = "0") the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator when it is unused by software. Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written. Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 s) is passed from the voltage comparator function become valid.
17
18
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SYMBOL
The symbols shown below are used in the following instruction function table and instruction list. Symbol A B DR E Q1 Q2 Q3 AD J1 SI V1 V2 I1 I2 W1 W2 W3 W4 W6 MR K0 PU0 FR0 X Y Z DP PC PCH PCL SK SP CY R1 R2 R3 R4 T1 T2 T3 T4 Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) A-D control register Q1 (4 bits) A-D control register Q2 (4 bits) Voltage comparator control register Q3 (4 bits) Successive comparison register AD (10 bits) Serial I/O mode register J1 (4 bits) Serial I/O register SI (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W6 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Pull-up control register PU0 (4 bits) Direction register FR0 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ! 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer 3 reload register Timer 4 reload register Timer 1 Timer 2 Timer 3 Timer 4 C + x
Note : The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
Contents
Symbol T1F T2F T3F T4F WDF1 WEF INTE EXF0 EXF1 P ADF SIOF D P0 P1 P2 P3 P4 P5 x y z p n i j A3A2A1A0
Contents Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A-D conversion completion flag Serial I/O transmission/reception completion flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (3 bits) Port P3 (4 bits) Port P4 (4 bits) Port P5 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others)
? () -- M(DP) a p, a
Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others)
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION
GroupMnemonic ing TAB TBA TAY TYA TEAB Register to register transfer Function (A) (B) RAM to register transfer (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) TABE (B) (E7-E4) (A) (E3-E0) TDA TAD (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 TAZ (A1, A0) (Z1, Z0) (A3, A2) 0 TAX TASP (A) (X) (A2-A0) (SP2-SP0) (A3) 0 LXY x, y RAM addresses Arithmetic operation (X) x, x = 0 to 15 (Y) y, y = 0 to 15 LZ z INY DEY TAM j (Z) z, z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1 SC (A) (M(DP)) (X) (X)EXOR(j) RAM to register transfer j = 0 to 15 SZC XAM j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 RAR XAMD j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 CY A3A2A1A0 CMA (CY) = 0 ? Return operation (A) (A) RTI (PC) (SK(SP)) (SP) (SP) - 1 RT (PC) (SK(SP)) (SP) (SP) - 1 RTS (PC) (SK(SP)) (SP) (SP) - 1 RC (CY) 0 (CY) 1 AM AMC TABP p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p Branch operation (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) BM a (A) (A) + (M(DP)) + (CY) (CY) Carry An (A) (A) + n n = 0 to 15 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) Subroutine operation BML p, a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) Ba BL p, a (PCL) a6-a0 (PCH) p (PCL) a6-a0 BLA p (PCH) p (PCL) (DR2-DR0, A3-A0) GroupMnemonic ing XAMI j Function (A) (M(DP)) (X) (X)EXOR(j) (Y) (Y) + 1 TMA j (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 Comparison operation LA n (A) n n = 0 to 15 SEAM SEA n Bit operation j = 0 to 15 RB j GroupMnemonic ing SB j Function (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15
AND OR
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing DI EI SNZ0 Function (INTE) 0 (INTE) 1 (EXF0) = 1 ? After skipping (EXF0) 0 SNZ1 (EXF1) = 1 ? After skipping (EXF1) 0 T1AB SNZI0 Interrupt operation I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ? SNZI1 I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ? TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAW1 TW1A TAW2 Timer operation TW2A TAW3 TW3A (A) (V1) T2AB (V1) (A) Timer operation (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (I2) (I2) (A) (A) (W1) T4AB (W1) (A) (A) (W2) (W2) (A) (A) (W3) TR3AB (W3) (A) (R37-R34) (B) (R33-R30) (A) SD (D(Y)) 1 (Y) = 0 to 7 SZD (D(Y)) = 0 ? (Y) = 0 to 7
*: The 4513 Group does not have these instructions.
GroupMnemonic ing TAW4 TW4A TAW6 TW6A TAB1
Function (A) (W4) (W4) (A) (A) (W6) (W6) (A) (B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A)
GroupMnemonic ing SNZT1
Function (T1F) = 1 ? After skipping (T1F) 0
SNZT2 Timer operation
(T2F) = 1 ? After skipping (T2F) 0
SNZT3
(T3F) = 1 ? After skipping (T3F) 0
SNZT4
(T4F) = 1 ? After skipping (T4F) 0
TAB2
(B) (T27-T24) (A) (T23-T20)
IAP0 OP0A
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A2-A0) (P22-P20) (A3) 0
(R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) OP1A IAP2 IAP1
TAB3
(B) (T37-T34) (A) (T33-T30)
T3AB
(R37-R34) (B) Input/Output operation (T37-T34) (B) (R33-R30) (A) (T33-T30) (A)
IAP3 OP3A IAP4* OP4A* IAP5* OP5A* CLD
(A) (P3) (P3) (A) (A) (P4) (P4) (A) (A) (P5) (P5) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 7
TAB4
(B) (T47-T44) (A) (T43-T40) (R47-R44) (B) (T47-T44) (B) (R43-R40) (A) (T43-T40) (A)
TR1AB
(R17-R14) (B) (R13-R10) (A)
RD
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TK0A Input/Output operation TAK0 TPU0A TAPU0 TFR0A* TABSI Function (K0) (A) (A) (K0) (PU0) (A) (A) (PU0) TALA (FR0) (A) (A) (SI3-SI0) (B) (SI7-SI4) TSIAB Serial I/O control operation (SI3-SI0) (A) (SI7-SI4) (B) TAJ1 TJ1A SST (A) (J1) (J1) (A) SNZAD (SIOF) 0 Serial I/O starting SNZSI (SIOF) = 1 ? After skipping (SIOF) 0 TQ2A NOP POF EPOF SNZP Other operation WRST TAMR TMRA TAQ3 TQ3A TAQ2 (ADF) = 1 ? After skipping (ADF) 0 (A) (Q2) (Q2) (A) (PC) (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? (WDF1) 0, (WEF) 1 (A) (MR) (MR) (A) (A) (Q3) (Q33, Q32) (A3, A2) (Q31) (CMP1 comparison result) (Q30) (CMP0 comparison result) A-D conversion operation TADAB Grouping Mnemonic TABAD Function (A) (AD5-AD2) (B) (AD9-AD6) However, in the comparator mode, (A) (AD3-AD0) (B) (AD7-AD4) (A) (AD1, AD0, 0, 0) (AD3-AD0) (A) (AD7-AD4) (B) (A) (Q1) (Q1) (A) (ADF) 0 A-D conversion starting
TAQ1 TQ1A ADST
*: The 4513 Group does not have these instructions.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (for 4513 Group)
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP - POF
01 BLA CLD -
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D
0E
0F BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL*** BL***
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - - - - - - - - SNZ0
TABP TABP TABP TABP BML BML*** BL 0 16*** 32** 48* TABP TABP TABP TABP BML BML*** BL 1 17*** 33** 49* TABP TABP TABP TABP BML BML*** BL 2 18*** 34** 50* TABP TABP TABP TABP BML BML*** BL 3 19*** 35** 51* TABP TABP TABP TABP BML BML*** BL 4 20*** 36** 52* TABP TABP TABP TABP BML BML*** BL 5 21*** 37** 53* TABP TABP TABP TABP BML BML*** BL 6 22*** 38** 54* TABP TABP TABP TABP BML BML*** BL 7 23*** 39** 55* TABP TABP TABP TABP BML BML*** BL 8 24*** 40** 56* TABP TABP TABP TABP BML BML*** BL 9 25*** 41** 57* TABP TABP TABP TABP BML BML*** BL 10 26*** 42** 58* TABP TABP TABP TABP BML BML*** BL 11 27*** 43** 59* TABP TABP TABP TABP BML BML*** BL 12 28*** 44** 60* TABP TABP TABP TABP BML BML*** BL 13 29*** 45** 61* TABP TABP TABP TABP BML BML*** BL 14 30*** 46** 62* TABP TABP TABP TABP BML BML*** BL 15 31*** 47** 63*
SNZP INY DI EI RC SC - - AM AMC TYA - TBA - RD SD - DEY AND OR
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
TDA SNZ1
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - SNZI1 - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 * *, **, and *** cannot be used in the M34513M2-XXXSP/FP. * * and ** cannot be used in the M34513M4-XXXSP/FP. * * and ** cannot be used in the M34513E4FP. * * cannot be used in the M34513M6-XXXFP.
BL BML BLA BMLA SEA SZD
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (continued) (for 4513 Group)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111
20 - - TJ1A - TQ1A TQ2A
21
22
23
24 - -
25
26
27
28
29 - - - - - - - - - - - - - - SST ADST
2A WRST - - - - - - - - - - - - - - -
2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15
2C
2D
2E
2F
30-3F
TW3A OP0A T1AB TW4A OP1A T2AB - -
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2
TAM XAM XAMI XAMD LXY 0 0 0 0 TAM XAM XAMI XAMD LXY 1 1 1 1 TAM XAM XAMI XAMD LXY 2 2 2 2 TAM XAM XAMI XAMD LXY 3 3 3 3 TAM XAM XAMI XAMD LXY 4 4 4 4 TAM XAM XAMI XAMD LXY 5 5 5 5 TAM XAM XAMI XAMD LXY 6 6 6 6 TAM XAM XAMI XAMD LXY 7 7 7 7 TAM XAM XAMI XAMD LXY 8 8 8 8 TAM XAM XAMI XAMD LXY 9 9 9 9 TAM XAM XAMI XAMD LXY 10 10 10 10 TAM XAM XAMI XAMD LXY 11 11 11 11 TAM XAM XAMI XAMD LXY 12 12 12 12 TAM XAM XAMI XAMD LXY 13 13 13 13 TAM XAM XAMI XAMD LXY 14 14 14 14 TAM XAM XAMI XAMD LXY 15 15 15 15
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 - TAI1 IAP3 TAB4 SNZT4 - - - - - - - - - - - - - - - - - - - SNZAD
TW6A OP3A T4AB - - - - - - - - - - - TPU0A - - - - - - TSIAB
TAQ1 TAI2 TAQ2 -
TQ3A TMRA - - - - - - - TW1A TW2A TI1A TI2A - - TK0A - - - -
TAQ3 TAK0 - - TAPU0 - - - - - - - -
TABSI SNZSI TABAD - - - - - - - - - - - - -
TADAB TALA - -
TR3AB TAW1 - - - TR1AB TAW2 TAW3 TAW4 -
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (for 4514 Group)
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP - POF
01 BLA CLD -
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - - - - - - - - SNZ0
TABP TABP TABP TABP BML 0 16 32 48* TABP TABP TABP TABP BML 1 17 33 49* TABP TABP TABP TABP BML 2 18 34 50* TABP TABP TABP TABP BML 3 19 35 51* TABP TABP TABP TABP BML 4 20 36 52* TABP TABP TABP TABP BML 5 21 37 53* TABP TABP TABP TABP BML 6 22 38 54* TABP TABP TABP TABP BML 7 23 39 55* TABP TABP TABP TABP BML 8 24 40 56* TABP TABP TABP TABP BML 9 25 41 57* TABP TABP TABP TABP BML 10 26 42 58* TABP TABP TABP TABP BML 11 27 43 59* TABP TABP TABP TABP BML 12 28 44 60* TABP TABP TABP TABP BML 13 29 45 61* TABP TABP TABP TABP BML 14 30 46 62* TABP TABP TABP TABP 15 31 47 63* BML
SNZP INY DI EI RC SC - - AM AMC TYA - TBA - RD SD - DEY AND OR
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
TDA SNZ1
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - SNZI1 - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 * * cannot be used in the M34514M6-XXXFP.
BL BML BLA BMLA SEA SZD
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (continued) (for 4514 Group)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111 30-3F
20 - - TJ1A - TQ1A TQ2A
21
22
23
24 - -
25
26
27
28
29 - - - - - - - - - - - - - - SST ADST
2A WRST - - - - - - - - - - - - - - -
2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15
2C
2D
2E
2F
TW3A OP0A T1AB TW4A OP1A T2AB - -
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2
TAM XAM XAMI XAMD LXY 0 0 0 0 TAM XAM XAMI XAMD LXY 1 1 1 1 TAM XAM XAMI XAMD LXY 2 2 2 2 TAM XAM XAMI XAMD LXY 3 3 3 3 TAM XAM XAMI XAMD LXY 4 4 4 4 TAM XAM XAMI XAMD LXY 5 5 5 5 TAM XAM XAMI XAMD LXY 6 6 6 6 TAM XAM XAMI XAMD LXY 7 7 7 7 TAM XAM XAMI XAMD LXY 8 8 8 8 TAM XAM XAMI XAMD LXY 9 9 9 9 TAM XAM XAMI XAMD LXY 10 10 10 10 TAM XAM XAMI XAMD LXY 11 11 11 11 TAM XAM XAMI XAMD LXY 12 12 12 12 TAM XAM XAMI XAMD LXY 13 13 13 13 TAM XAM XAMI XAMD LXY 14 14 14 14 TAM XAM XAMI XAMD LXY 15 15 15 15
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 - TAI1 IAP3 TAB4 SNZT4 - - - - - - - SNZAD
TW6A OP3A T4AB - - OP4A OP5A - - - - - -
TAQ1 TAI2 IAP4 TAQ2 - IAP5 - - - - - - - - - -
TQ3A TMRA - - - - - - - TW1A TW2A TI1A
TAQ3 TAK0 - - TAPU0 - - - - - - - -
TI2A TFR0A TSIAB - - TK0A - - - - - - - - TPU0A - -
TABSI SNZSI TABAD - - - - - - - - - - - - -
TADAB TALA - -
TR3AB TAW1 - - - TR1AB TAW2 TAW3 TAW4 -
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0
01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x, x = 0 to 15 (Y) y, y = 0 to 15 (Z) z, z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1
Register to register transfer
TEAB TABE TDA TAD TAZ TAX TASP LXY x, y
x3 x2 x1 x0 y3 y2 y1 y0
RAM addresses
LZ z INY DEY
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 1 1
1 0 0
0 0 1
z1 z0 1 1 1 1
048 +z 013 017
1 1 1
1 1 1
TAM j XAM j RAM to register transfer XAMD j
1 1 1
0 0 0
1 1 1
1 1 1
0 0 1
0 1 1
j j j
j j j
j j j
j j j
2Cj 2Dj 2Fj
1 1 1
1 1 1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
XAMI j
1
0
1
1
1
0
j
j
j
j
2Ej
1
1
TMA j
1
0
1
0
1
1
j
j
j
j
2Bj
1
1
68
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - Continuous description - (Y) = 0 (Y) = 15
- - - - - - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Transfers the contents of register D to register A. Transfers the contents of register Z to register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
- - -
- - (Y) = 15
- - -
(Y) = 0
-
-
-
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n
07n
1
1
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (Note) (A) (A) + (M(DP)) (A) (A) + (M(DP)) +(CY) (CY) Carry (A) (A) + n n = 0 to 15 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
08p +p
1
3
AM Arithmetic operation AMC An
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 0
1 1 n
0 0 n
1 1 n
0 1 n
00A 00B 06n
1 1 1
1 1 1
AND OR SC RC SZC CMA RAR SB j
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0 0 0 1
0 0 0 0 1 0 0 0 0 1 1 1 1
1 1 0 0 0 1 1 1 0 0 0 0 1
1 1 0 0 1 1 1 1 1 0 0 0 n
0 0 1 1 1 1 1 1 1 0 1 1 n
0 0 1 1 1 0 0 j j j 1 0 n
0 1 1 0 1 0 1 j j j 0 1 n
018 019 007 006 02F 01C 01D 05C +j 04C +j 02j 026 025 07n
1 1 1 1 1 1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 2
Bit operation 70 Comparison operation
RB j SZB j SEAM SEA n
Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8.
MITSUBISHI MICROCOMPUTERS
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
Continuous description -
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used.
-
- - Overflow = 0
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. - Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
- - - - (CY) = 0 - - - - (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n
- - 1 0 - -
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - - - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
71
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 0 0 0 1 1 1 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0
18a +a 0Ep +p 2pa +a 010 2pp 1aa
1 2
1 2
(PCL) a6-a0 (PCH) p (PCL) a6-a0 (Note)
Branch operation
p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 0 0 0 0
2
2
p5 p4 0 0
p3 p2 p1 p0
(PCH) p (PCL) (DR2-DR0, A3-A0) (Note) (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 (Note) (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0,A3-A0) (Note) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (INTE) 0 (INTE) 1 (EXF0) = 1 ? After skipping (EXF0) 0 (EXF1) = 1 ? After skipping (EXF1) 0
a6 a5 a4 a3 a2 a1 a0
1
1
Subroutine operation
BML p, a
0 1
0 0 0 0
1
1
0
p4 p3 p2 p1 p0
0Cp +p 2pa +a 030 2pp
2
2
p5 a6 a5 a4 a3 a2 a1 a0 0 0 1 1 0 0 0 0 0
BMLA p
0 1
2
2
p5 p4 0
p3 p2 p1 p0
RTI Return operation
0
0
0
1
0
0
0
1
1
0
046
1
1
RT RTS DI
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 1 0 0 0
0 0 0 0 1
0 0 0 0 1
0 0 0 0 1
1 1 1 1 0
0 0 0 0 0
0 1 0 1 0
044 045 004 005 038
1 1 1 1 1
2 2 1 1 1
Interrupt operation
EI SNZ0
SNZ1
0
0
0
0
1
1
1
0
0
1
039
1
1
Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8.
72
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
- -
- -
Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Clears (0) to the interrupt enable flag INTE, and disables the interrupt. Sets (1) to the interrupt enable flag INTE, and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is "1." After skipping, clears (0) to the EXF0 flag. Skips the next instruction when the contents of EXF1 flag is "1." After skipping, clears (0) to the EXF1 flag.
- Skip at uncondition - - (EXF0) = 1
- - - - -
(EXF1) = 1
-
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZI0 0 0 0 0 1 1 1 0 1 0
03A
1
1
I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ?
SNZI1
0
0
0
0
1
1
1
0
1
1
03B
1
1
I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ?
Interrupt operation
TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAW1 TW1A TAW2
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1
0 1 0 1 0 0 0 1 1 1 1 1 1 0 1 0 0 0
1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0
0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 0 0 1
0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 1
054 03F 055 03E 253 217 254 218 24B 20E 24C 20F 24D 210 24E 211 250 213
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (I2) (I2) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A) (A) (W6) (W6) (A)
Timer operation 74
TW2A TAW3 TW3A TAW4 TW4A TAW6 TW6A
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
(INT0) = "H" However, I12 = 1 (INT0) = "L" However, I12 = 0 (INT1) = "H" However, I22 = 1 (INT1) = "L" However, I22 = 0 - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - -
When bit 2 (I12) of register I1 is "1" : Skips the next instruction when the level of INT0 pin is "H." When bit 2 (I12) of register I1 is "0" : Skips the next instruction when the level of INT0 pin is "L." When bit 2 (I22) of register I2 is "1" : Skips the next instruction when the level of INT1 pin is "H." When bit 2 (I22) of register I2 is "0" : Skips the next instruction when the level of INT1 pin is "L." Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB1 T1AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0
270 230
1 1
1 1
(B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (B) (T27-T24) (A) (T23-T20) (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) (B) (T37-T34) (A) (T33-T30) (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) (B) (T47-T44) (A) (T43-T40) (R47-R44) (B) (T47-T44) (B) (R43-R40) (A) (T43-T40) (A) (R17-R14) (B) (R13-R10) (A) (R37-R34) (B) (R33-R30) (A) (T1F) = 1 ? After skipping (T1F) 0 (T2F) = 1 ? After skipping (T2F) 0 (T3F) = 1 ? After skipping (T3F) 0 (T4F) = 1 ? After skipping (T4F) 0
TAB2 T2AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
1 1
271 231
1 1
1 1
TAB3 T3AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
0 0
272 232
1 1
1 1
Timer operation
TAB4 T4AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
1 1
273 233
1 1
1 1
TR1AB TR3AB SNZT1
1 1 1
0 0 0
0 0 1
0 0 0
1 1 0
1 1 0
1 1 0
1 0 0
1 1 0
1 1 0
23F 23B 280
1 1 1
1 1 1
SNZT2
1
0
1
0
0
0
0
0
0
1
281
1
1
SNZT3
1
0
1
0
0
0
0
0
1
0
282
1
1
SNZT4
1
0
1
0
0
0
0
0
1
1
283
1
1
76
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
- -
- -
Transfers the contents of timer 1 to registers A and B. Transfers the contents of registers A and B to timer 1 and timer 1 reload register.
- -
- -
Transfers the contents of timer 2 to registers A and B. Transfers the contents of registers A and B to timer 2 and timer 2 reload register.
- -
- -
Transfers the contents of timer 3 to registers A and B. Transfers the contents of registers A and B to timer 3 and timer 3 reload register.
- -
- -
Transfers the contents of timer 4 to registers A and B. Transfers the contents of registers A and B to timer 4 and timer 4 reload register.
- - (T1F) = 1
- - -
Transfers the contents of registers A and B to timer 1 reload register. Transfers the contents of registers A and B to timer 3 reload register. Skips the next instruction when the contents of T1F flag is "1." After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of T2F flag is "1." After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of T3F flag is "1." After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of T4F flag is "1." After skipping, clears (0) to T4F flag.
(T2F) =1
-
(T3F) = 1
-
(T4F) = 1
-
77
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4* OP4A* 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 TK0A TAK0 TPU0A TAPU0 TFR0A* 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0
260 220 261 221 262 263 223 264 224 265 225 011 014 015 024 02B 21B 256 22D 257 228
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A2-A0) (P22-P20) (A3) 0 (A) (P3) (P3) (A) (A) (P4) (P4) (A) (A) (P5) (P5) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 7 (D(Y)) 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7
Input/Output operation
IAP5* OP5A* CLD RD SD SZD
1 1 1 1 1
1 1 1 1 1
(K0) (A) (A) (K0) (PU0) (A) (A) (PU0) (FR0) (A)
*: The 4513 Group does not have these instructions.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - - - - (D(Y)) = 0 (Y) = 0 to 7
- - - - - - - - - - - - - - -
Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P4 to register A. Outputs the contents of register A to port P4. Transfers the input of port P5 to register A. Outputs the contents of register A to port P5. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is "0."
- - - - -
- - - - -
Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to direction register FR0.
79
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TABSI 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0
278 238 242 202 29E 288
1 1 1 1 1 1
1 1 1 1 1 1
(A) (SI3-SI0) (B) (SI7-SI4) (SI3-SI0) (A) (SI7-SI4) (B) (A) (J1) (J1) (A) (SIOF) 0 Serial I/O starting (SIOF) = 1 ? After skipping (SIOF) 0 (A) (AD5-AD2) (B) (AD9-AD6) However, in the comparator mode, (A) (AD3-AD0) (B) (AD7-AD4) (A) (AD1, AD0, 0, 0) (AD3-AD0) (A) (AD7-AD4) (B) (A) (Q1) (Q1) (A) (ADF) 0 A-D conversion starting (ADF) = 1 ? After skipping (ADF) 0 (A) (Q2) (Q2) (A) (PC) (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? (WDF1) 0 (WEF) 1 (A) (MR) (MR) (A) (A) (Q3) (Q33, Q32) (A3, A2) (Q31) (CMP1 comparison result) (Q30) (CMP0 comparison result)
Serial I/O control operation
TSIAB TAJ1 TJ1A SST SNZSI
TABAD
1
0
0
1
1
1
1
0
0
1
279
1
1
TALA A-D conversion operation TADAB TAQ1 TQ1A ADST SNZAD
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 1 1
1 0 1 0 0 0
0 1 0 0 0 0
0 1 0 0 1 0
1 1 0 0 1 0
0 0 1 1 1 1
0 0 0 0 1 1
1 1 0 0 1 1
249 239 244 204 29F 287
1 1 1 1 1 1
1 1 1 1 1 1
TAQ2 TQ2A NOP POF EPOF Other operation SNZP WRST TAMR TMRA TAQ3 TQ3A
1 1 0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 1 0 1 0
0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 1 1 0 0
0 0 0 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 1 1 1
0 0 0 1 1 1 0 1 1 1 1
1 1 0 0 1 1 0 0 0 0 0
245 205 000 002 05B 003 2A0 252 216 246 206
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
80
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Carry flag CY
Datailed description
- - - - - (SIOF) = 1
- - - - - -
Transfers the contents of serial I/O register SI to registers A and B. Transfers the contents of registers A and B to serial I/O register SI. Transfers the contents of serial I/O mode register J1 to register A. Transfers the contents of register A to serial I/O mode register J1. Clears (0) to SIOF flag and starts serial I/O. Skips the next instruction when the contents of SIOF flag is "1." After skipping, clears (0) to SIOF flag. Transfers the high-order 8 bits of the contents of register AD to registers A and B.
-
-
- - - - - (ADF) = 1
- - - - - -
Transfers the low-order 2 bits of the contents of register AD to the high-order 2 bits of the contents of register A. Simultaneously, the low-order 2 bits of the contents of the register A is "0." Transfers the contents of registers A and B to the comparator register at the comparator mode. Transfers the contents of the A-D control register Q1 to register A. Transfers the contents of register A to the A-D control register Q1. Clears the ADF flag, and the A-D conversion at the A-D conversion mode or the comparator operation at the comparator mode is started. Skips the next instruction when the contents of ADF flag is "1". After skipping, clears (0) the contents of ADF flag. Transfers the contents of the A-D control register Q2 to register A. Transfers the contents of register A to the A-D control register Q2. No operation Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Makes the immediate POF instruction valid by executing the EPOF instruction. Skips the next instruction when P flag is "1". After skipping, P flag remains unchanged. Operates the watchdog timer and initializes the watchdog timer flag WDF1. Transfers the contents of the clock control register MR to register A. Transfers the contents of register A to the clock control register MR. Transfers the contents of the voltage comparator control register Q3 to register A. Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits of the register Q3.
- - - - - (P) = 1 - - - - -
- - - - - - - - - - -
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register I1 I13 Not used 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) at reset : 00002 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT0 pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT0 pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled at reset : 00002 at RAM back-up : state retained R/W
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit Interrupt control register I2
I23
Not used
0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT1 pin is recognized with the SNZI1 instruction)/"L" level Rising waveform ("H" level of INT1 pin is recognized with the SNZI1 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Not used 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected at reset : 00002 at RAM back-up : state retained R/W
0 Stop (state retained) 1 Operating 0 This bit has no function, but read/write is enabled. 1 W21 W20 Count source 0 0 1 1 0 1 0 1 Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal at RAM back-up : state retained R/W
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits W30 Timer 3 control bit Timer 3 count start synchronous circuit control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Count source Timer 2 underflow signal Prescaler output Not available Not available at RAM back-up : state retained R/W
Timer control register W4 W43 W42 W41 Timer 4 count source selection bits W40 Timer 4 control bit Not used 0 1 0 1
at reset : 00002
Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available at RAM back-up : state retained R/W
W41 W40 0 0 0 1 1 0 1 1
Timer control register W6 W63 W62 W61 W60 CNTR1 output control bit D7/CNTR1 function selection bit CNTR0 output control bit D6/CNTR0 output control bit 0 1 0 1 0 1 0 1
at reset : 00002
Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input)
Note: "R" represents read enabled, and "W" represents write enabled.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Serial I/O mode register J1 J13 J12 J11 J10 Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit Serial I/O synchronous clock selection bit A-D control register Q1 Q13 Note used 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20, P21, P22 selected Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8) at reset : 00002 at RAM back-up : state retained R/W
Q12
Q11
Analog input pin selection bits (Note 2)
Q10
0 1 Q12Q11 Q10 000 001 010 011 100 101 110 111
This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at RAM back-up : state retained R/W
A-D control register Q2 Q23 Q22 Q21 Q20 A-D operation mode selection bit P43/AIN7 and P42/AIN6 pin function selection bit (Not used for the 4513 Group) P41/AIN5 pin function selection bit (Not used for the 4513 Group) P40/AIN4 pin function selection bit (Not used for the 4513 Group) Comparator control register Q3 (Note 3) Q33 Q32 Q31 Q30 Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit CMP1 comparison result store bit CMP0 comparison reslut store bit Clock control register MR MR3 MR2 MR1 MR0 System clock selection bit Not used Not used Not used 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002 A-D conversion mode Comparator mode P43, P42
(read/write enabled for the 4513 Group)
AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 P40 AIN4/P40 at reset : 00002 (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group) (read/write enabled for the 4513 Group) at RAM back-up : state retained R/W
Voltage comparator (CMP1) invalid Voltage comparator (CMP1) valid Voltage comparator (CMP0) invalid Voltage comparator (CMP0) valid CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+ at reset : 10002 f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. at RAM back-up : 10002 R/W
Notes 1: "R" represents read enabled, "W" represents write enabled. 2: Select AIN4-AIN7 with register Q1 after setting register Q2. 3: Bits 0 and 1 of register Q3 can be only read.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Pull-up control register PU0 PU03 PU02 PU01 PU00 Pins P12 and P13 pull-up transistor control bit Pins P10 and P11 pull-up transistor control bit Pins P02 and P03 pull-up transistor control bit Pins P00 and P01 pull-up transistor control bit Direction register FR0 (Note 2) FR03 FR02 FR01 FR00 Port P53 input/output control bit Port P52 input/output control bit Port P51 input/output control bit Port P50 input/output control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Port P53 input Port P53 output Port P52 input Port P52 output Port P51 input Port P51 output Port P50 input Port P50 output at RAM back-up : state retained W at RAM back-up : state retained R/W
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: The 4513 Group does not have the direction register FR0.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, RESET, XIN, VDCE Input voltage D0-D7 Input voltage AIN0-AIN7 Output voltage P0, P1, P3, P4, P5, RESET Output voltage D0-D7 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Output transistors in cut-off state Conditions Ratings -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to 13 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to 13 -0.3 to VDD+0.3 Package: 42P2R Ta = 25 C Package: 32P6B Package: 32P4B 300 300 1100 -20 to 85 -40 to 125 C C Unit V V V V V V V mW
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version:Ta = -20 C to 85 C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 85 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Mask ROM version Middle-speed mode Mask ROM version VDD Supply voltage High-speed mode One Time PROM version Middle-speed mode f(XIN) 4.2 MHz f(XIN) 3.0 MHz f(XIN) 4.2 MHz f(XIN) 2.0 MHz f(XIN) 1.5 MHz f(XIN) 4.2 MHz Limits Min. 2.5 2.0 4.0 2.5 2.0 2.5 4.0 2.5 1.8 2.0 0 P0, P1, P2, P3, P4, P5, XIN, VDCE D0-D7
RESET
Typ.
Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Unit
V
One Time PROM version f(XIN) 4.2 MHz f(XIN) 2.0 MHz High-speed mode VRAM VSS VIH VIH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOL(avg) IOH(avg) IOL(avg) RAM back-up voltage (at RAM back-up mode) Supply voltage "H" level input voltage "H" level input voltage "H" level input voltage "H" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "H" level peak output current "H" level average output current "L" level peak output current "L" level peak output current "L" level peak output current "L" level peak output current "L" level average output current "L" level average output current "L" level average output current "L" level average output current "H" level total average current "L" level total average current Mask ROM version One Time PROM version
V V VDD 12 VDD VDD 0.2VDD 0.3VDD 0.15VDD V V V V V V V mA mA 10 4 40 30 24 12 24 12 5 2 30 15 15 7 12 6 mA mA mA mA mA mA mA mA
0.8VDD 0.8VDD 0.85VDD 0.85VDD 0 0 0 -20 -10 -10 -5
CNTR0, CNTR1, SIN, SCK, INT0, INT1 P0, P1, P2, P3, P4, P5, D0-D7, XIN, VDCE
RESET
CNTR0, CNTR1, SIN, SCK, INT0, INT1 VDD = 5.0 V P5 VDD = 3.0 V P5 (Note) P3, RESET D6, D7 D0-D5 P0, P1, P4, P5, SCK, SOUT P3, RESET (Note) D6, D7 (Note) D0-D5 (Note) P0, P1, P4, P5, SCK, SOUT (Note) P5 P5, D, RESET, SCK, SOUT P0, P1, P3, P4 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V
-30 80 80 mA
Note: The average output current (IOH, IOL) is the average value during 100 ms.
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version:Ta = -20 C to 85 C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 85 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Mask ROM version Middle-speed mode Oscillation frequency (with a ceramic resonator) One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version tw(SCK) Serial I/O external clock period ("H" and "L" pulse width) Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version tw(CNTR) Timer external input period ("H" and "L" pulse width) Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Conditions VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V 1.5 3.0 4.0 1.5 3.0 750 1.5 2.0 750 1.5 1.5 3.0 4.0 1.5 3.0 750 1.5 2.0 750 1.5 ns ns Min. Limits Typ. Max. 4.2 3.0 4.2 4.2 2.0 1.5 4.2 2.0 3.0 3.0 3.0 1.0 0.8 3.0 1.0 MHz MHz Unit
f(XIN)
f(XIN)
Oscillation frequency (with external clock input)
s
s
ns s
s
s
ns s
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
(Mask ROM version:Ta = -20 C to 85 C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 85 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol VOH VOL VOL Parameter "H" level output voltage P5 "L" level output voltage P0, P1, P4, P5 "L" level output voltage P3, RESET VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VOL "L" level output voltage D6, D7 VDD = 3 V VOL IIH IIH IIL IIL "L" level output voltage D0-D5 "H" level input current P0, P1, P2, P3, P4, P5, RESET, VDCE "H" level input current D0-D7 "L" level input current P0, P1, P2, P3, P4, P5, RESET, VDCE "L" level input current D0-D7 at active mode VDD = 5 V VDD = 3 V VI = VDD, port P4 selected, port P5: input state VI = 12 V VI = 0 V No pull-up of ports P0 and P1, port P4 selected, port P5: input state VI = 0 V VDD = 5 V Middle-speed mode VDD = 3 V Middle-speed mode VDD = 5 V IDD Supply current High-speed mode VDD = 3 V at RAM back-up mode High-speed mode Ta = 25 C VDD = 5 V VDD = 3 V RPU VT+ - VT- Pull-up resistor value Hysteresis INT0, INT1, CNTR0, CNTR1, SIN, SCK VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VI = 0 V 20 40 50 100 0.3 0.3 1.5 0.6 f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 2.0 MHz f(XIN) = 400 kHz Test conditions IOH = -10 mA IOH = -5 mA IOL = 12 mA IOL = 6 mA IOL = 5 mA IOL = 2 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5 mA IOL = 15 mA IOL = 3 mA Limits Min. 3 2 Typ. Max. Unit V 2 0.9 2 0.9 2 0.9 2 0.9 2 0.9 1 1 -1 -1 1.8 0.5 0.9 0.2 3.0 0.6 0.9 0.3 0.1 5.5 1.5 2.7 0.6 9.0 1.8 2.7 0.9 1 10 6 125 250 mA V V V V V
A A A A
A
k V V
VT+ - VT- Hysteresis RESET
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A-D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode included, Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VIA f(XIN) Parameter Supply voltage Analog input voltage Oscillation frequency Middle-speed mode, VDD 2.7 V High-speed mode, VDD 2.7 V Conditions Min. 2.7 0 0.8 0.4 Limits Typ. Max. 5.5 VDD Unit V V MHz MHz
A-D CONVERTER CHARACTERISTICS
(Ta = -20 C to 85 C, unless otherwise noted) Symbol - - - V0T VFST IADD TCONV - - - Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage A-D operating current A-D conversion time Comparator resolution Comparator error (Note) Comparator comparison time Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -25 C to 85 C, VDD = 3.0 V to 5.5 V Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -25 C to 85 C, VDD = 3.0 V to 5.5 V VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V VDD = 5.0 V VDD = 3.0 V f(XIN) = 0.4 MHz to 4.0 MHz f(XIN) = 0.4 MHz to 2.0 MHz 0 0 5105 3060 5 3 5115 3069 0.7 0.2 Test conditions Min. Limits Typ. Max. 10 2 0.9 20 15 5125 3075 2.0 0.4 93.0 46.5 8 20 15 12 6 Unit bits LSB LSB mV mV mA
f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode Comparator mode VDD = 5.12 V VDD = 3.072 V f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode
s
bits mV
s
Note: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref Vref = VDD 256 !n
n = Value of register AD (n = 0 to 255)
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = -20 C to 85 C, unless otherwise noted) Symbol VRST IRST Parameter Detection voltage Operation current of voltage drop detection circuit Test conditions Min. 2.7 3.3 Limits Typ. 3.5 50 Max. 4.1 3.7 100 Unit V
Ta = 25 C VDD = 5.0 V
A
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE COMPARATOR RECOMMENDED OPERATING CONDITION
(Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VINCMP tCMP Parameter Supply voltage Voltage comparator input voltage Voltage comparator response time VDD = 3.0 V to 5.5 V VDD = 3.0 V to 5.5 V Conditions Min. 3.0 0.3VDD Limits Typ. Max. 5.5 0.7VDD 20 Unit V V s
VOLTAGE COMPARATOR CHARACTERISTICS
(Ta = -20 C to 85 C, VDD = 3.0 V to 5.5 V, unless otherwise noted) Symbol - ICMP Parameter Comparison decision voltage error Voltage comparator operation current Test conditions CMP0- > CMP0+, CMP0- < CMP0+ CMP1- > CMP1+, CMP1- < CMP1+ VDD = 5.0 V Min. Limits Typ. 20 15 Max. 100 50 Unit mV
A
BASIC TIMING DIAGRAM
Machine cycle Parameter Clock
Pin name XIN System clock = f(XIN) XIN System clock = f(XIN)/2 Mi Mi+1
Port D output Port D input Ports P0, P1, P3, P4, P5 output
D0-D7 D0-D7 P00-P03 P10-P13 P30-P33 P40-P43 P50-P53
Ports P0, P1, P2, P3, P00-P03 P10-P13 P4, P5 input P20-P22
P30-P33 P40-P43 P50-P53
Interrupt input
INT0,INT1
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4513/4514 Group has programmable ROM version software compatible with mask ROM. The built-in PROM of One Time PROM version can be written to and not be erased. The built-in PROM versions have functions similar to those of the mask ROM versions, but they have PROM mode that enables writing to built-in PROM. Table 25 shows the product of built-in PROM version. Figure 49 and 50 show the pin configurations of built-in PROM versions. Table 25 Product of built-in PROM version Product M34513E4SP/FP M34513E8FP M34514E8FP PROM size (! 10 bits) 4096 words 8192 words 8192 words RAM size (! 4 bits) 256 words 384 words 384 words Package SP: 32P4B FP: 32P6B-A 32P6B-A 42P2R-A ROM type One Time PROM version [shipped in blank]
D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS
1 2 3 4 5
32 31 30 29 28
P13 P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+ AIN0/CMP0P31/INT1 P30/INT0 VDCE VDD
P13 1 D0
2
42 P12 41 P11 40 P10 39 P03 38 P02 37 P01 36 P00 35 P43/AIN7 34 P42/AIN6 33 P41/AIN5 32 P40/AIN4 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP027 P33 26 P32 25 P31/INT1 24 P30/INT0 23 VDCE 22 VDD
D1 3 D2 4 D3 D4
5 6
M34513E4SP
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
D5 7 D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK P21/SOUT
14 15
M34514E8FP
P22/SIN 16 RESET 17 CNVSS 18 XOUT
19
Outline 32P4B
XIN 20
29 P13 26 P10 28 P12 25 P03 27 P11 31 D1 30 D0 32 D2
VSS 21
D3 1 D4 2 D5 3 D6/CNTR0 4 D7/CNTR1 5 P20/SCK 6 P21/SOUT 7 P22/SIN 8
24 P02 23 P01 22 P00
Outline 42P2R-A
M34513ExFP
21 20 19 18
AIN3/CMP1+ AIN2/CMP1AIN1/CMP0+
Fig. 50 Pin configuration of built-in PROM version of 4514 Group
AIN0/CMP017 P31/INT1
Outline 32P6B-A
Fig. 49 Pin configuration of built-in PROM version of 4513 Group
92
P30/INT0 16
11
VDD 14
VSS 13
XIN 12
CNVSS 10
RESET 9
XOUT
VDCE 15
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapters are listed in Table 26.Contact addresses at the end of this sheet for the appropriate PROM programmer. * Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 51.
Table 26 Programming adapters Microcomputer M34513E4SP M34513E4FP, M34513E8FP M34514E8FP Programming adapter PCA7442SP PCA7442FP PCA7441
Address 000016 1FFF16
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
(2) Notes on handling
A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 52 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped).
400016 5FFF16
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
7FFF16 Set "FF16" to the shaded area.
Fig. 51 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
Fig. 52 Flow of writing and test of the product shipped in blank
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH52-45B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M2-XXXSP/FP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 2.00K 07FF16 400016 2.00K 47FF16 FFFF
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M2-XXXSP M34513M2-XXXFP (hexadecimal notation)
Checksum code for entire EPROM area
EPROM Type: 27C256 27C512
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M2-XXXSP, 32P6B-A for M34513M2-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
,,, ,,, ,,,
, ,,,,, , , ,,,,, ,
High-order 5-bit data Low-order 5-bit data
000016 2.00K 07FF16 400016 2.00K 47FF16 7FFF
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
94
Issuance signature
Responsible Supervisor officer
MITSUBISHI MICROCOMPUTERS
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH52-44B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M4-XXXSP/FP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 4.00K 0FFF16 400016 4.00K 4FFF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name TEL ( Date issued Date:
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M4-XXXSP M34513M4-XXXFP (hexadecimal notation)
Checksum code for entire EPROM area
EPROM Type: 27C256 27C512
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M4-XXXSP, 32P6B-A for M34513M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
000016 4.00K 0FFF16 400016 4.00K 4FFF16 7FFF16
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
Issuance signature
V Customer
Responsible Supervisor officer
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4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH53-01B <85A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M6-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 6.00K 17FF16 400016 6.00K 57FF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name TEL ( Date issued Date:
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type: 27C256 27C512
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
000016 6.00K 17FF16 400016 6.00K 57FF16 7FFF16
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
96
Issuance signature
V Customer
Responsible Supervisor officer
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n atio ific t to pec c al s subje n a fi re not mits a li s is Thi etric m ice: Not e para Somnge. cha
.
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH52-99B <85A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 8.00K 1FFF16 400016 8.00K 5FFF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name TEL ( Date issued Date:
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type: 27C256
Low-order 5-bit data
27C512
Low-order 5-bit data
000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16
High-order 5-bit data
High-order 5-bit data
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
Issuance signature
V Customer
Responsible Supervisor officer
97
MITSUBISHI MICROCOMPUTERS
RY INA IM REL P
n atio ific t to pec c al s subje n a fi re not mits a li s is Thi etric m ice: Not e para Somnge. cha
.
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH52-41B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M6-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 6.00K 17FF16 400016 6.00K 57FF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name TEL ( Date issued Date:
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
27C512
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
000016 6.00K 17FF16 400016 6.00K 57FF16 7FFF16
,,, ,,, ,,,
Low-order 5-bit data High-order 5-bit data
98
Issuance signature
V Customer
Responsible Supervisor officer
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n atio ific t to pec c al s subje n a fi re not mits a li s is Thi etric m ice: Not e para Somnge. cha
.
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH52-40B <81A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V .
Mask ROM number Date: Receipt ) 000016 8.00K 1FFF16 400016 8.00K 5FFF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
Low-order 5-bit data
27C512
Low-order 5-bit data
000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16
High-order 5-bit data
High-order 5-bit data
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
Issuance signature
Responsible Supervisor officer
99
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n. atio ific pec ject to s ub nal a fi are s not its is is ric lim Th et m ice: Not e para om e. S ng cha
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
32
17
Mitsubishi lot number (6-digit or 7-digit)
Mitsubishi IC catalog name
1
16
B. Customer's Parts Number + Mitsubishi catalog name
32
17
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
1
Note1 : 2: 3: 4:
16
The mark field should be written right aligned. The fonts and size of characters are standard Mitsubishi type. Customer's Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), and (commas) are usable. If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required
.
,
C. Special Mark Required
32
17
1
16
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the Special logo required box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo.
100
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n. atio ific pec ject to s ub nal a fi are s not its is is ric lim Th et m ice: Not e para om e. S ng cha
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
32P6B (32-PIN LQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
24 25 17 16
Mitsubishi IC catalog name Mitsubishi IC catalog name
Mitsubishi lot number (4-digit or 5-digit)
32 1 8
9
B. Customer's Parts Number + Mitsubishi catalog name
24 25 17 16
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 7 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable.
.
,
32 1 8
9
101
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n. atio ific pec ject to s ub nal a fi are s not its is is ric lim Th et m ice: Not e para om e. S ng cha
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
42 22
Mitsubishi IC catalog name Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
1 21
B. Customer's Parts Number + Mitsubishi catalog name
42
22
Mitsubishi lot number (6-digit or 7-digit)
1 21
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 11 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required
.
,
C. Special Mark Required
42 22
1
21
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
102
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n. atio ific pec ject to s ub nal a fi are s not its is is ric lim Th et m ice: Not e para om e. S ng cha
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
32P4B
EIAJ Package Code SDIP32-P-400-1.78 JEDEC Code - Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy
Plastic 32pin 400mil SDIP
32
17
1
16
D
Symbol A A1 A2 b b1 b2 c D E e e1 L
e SEATING PLANE
b1
b
b2
Dimension in Millimeters Min Nom Max - - 5.08 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 - 1.778 - - 10.16 - 3.0 - - 0 - 15
A
32P6B-A
EIAJ Package Code LQFP32-P-77-0.80 JEDEC Code - Weight(g) Lead Material Alloy 42
L
A1
A2
Plastic 32pin 7!7mm body LQFP
MD
32
25
b2
HD D
e
I2
1 24
Recommended Mount Pad
E HE
Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME
8
17
9
16
A L1 e F
b
A1
y
L Detail F
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 1.4 - - 0.3 0.35 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - 0.5 - - - - 1.0 - - 7.4 - - 7.4
A2
c
ME
e1
E
c
103
MITSUBISHI MICROCOMPUTERS
Y NAR MI ELI PR
n. atio ific pec ject to s ub nal a fi are s not its is is ric lim Th et m ice: Not e para om e. S ng cha
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
42P2R-A
EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code - Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 450mil SSOP
e
42 22
b2
HE
E
e1
F
Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max - - 2.4 0.05 - - - 2.0 - 0.35 0.4 0.5 0.13 0.15 0.2 17.3 17.5 17.7 8.2 8.4 8.6 - 0.8 - 11.63 11.93 12.23 0.3 0.5 0.7 - 1.765 - - - 0.15 0 - 10 - 0.5 - - 11.43 - - 1.27 -
1
21
A
D
A2
A1
L1
e
y
b
c Detail F
L
A A1 A2 b c D E e HE L L1 y b2 e1 I2
104
I2
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Aug. 1998. Specifications subject to change without notice.

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